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AMD has officially confirmed the processor enthusiasts have been waiting months for. The Ryzen 9 9950X3D2 Dual Edition is the world’s first desktop chip to feature 3D V-Cache on both compute chiplets, and it arrives April 22nd.
There have been few processor announcements in recent memory that felt genuinely, structurally different from what came before. AMD’s Ryzen 9 9950X3D2 Dual Edition is one of them. Announced this morning by Jack Huynh, AMD’s SVP and GM of Computing and Graphics, through a video posted to AMD’s YouTube channel, this chip does something no desktop processor has ever done: it applies 3D V-Cache technology across both of its compute chiplets simultaneously, not just one.
The result is 208MB of total on-chip cache, comprising 192MB of L3 and 16MB of L2. That is the highest cache figure ever shipped in a consumer Ryzen processor, and AMD is not shy about leaning into that record. Full official specifications are available on the AMD product page.
What Is Dual 3D V-Cache, Exactly?
To understand why this matters, a quick bit of context helps. AMD’s 3D V-Cache technology works by stacking additional SRAM directly on top of a compute chiplet via through-silicon vias. Previous X3D processors, including the Ryzen 9 9950X3D, applied this extra cache to only one of the two CCDs in a dual-chiplet design. The second CCD ran with standard cache allocations. That asymmetry created real-world trade-offs, with certain workloads performing better depending on which CCD a task was scheduled to.
The 9950X3D2 eliminates that compromise entirely. Both CCDs now carry stacked V-Cache, meaning every core on the chip has equal access to the expanded cache pool. A useful way to picture it: imagine two Ryzen 7 9850X3D processors fused onto a single package. That is essentially what AMD has engineered here.
“208MB of cache means more game data, more assets, and more working data sitting right next to the CPU cores.” — Jack Huynh, AMD SVP
Specifications at a Glance
Architecture
Zen 5 (Granite Ridge)
Cores / Threads
16 / 32
Base / Boost Clock
4.3 GHz / Up to 5.6 GHz
L1 / L2 / L3 Cache
1280 KB / 16 MB / 192 MB
Total Cache
208 MB
3D V-Cache
Both CCDs (second-generation)
TDP
200W
Socket
AM5
Memory
DDR5, up to 256 GB
PCIe Version
PCIe 5.0
Instruction Set Extensions
AVX-512, AVX2, AES-NI
Cooler Included
No (liquid cooler recommended)
Overclocking
Unlocked
Launch Date
April 22, 2026
Price
TBA
Performance Claims and Target Workloads
AMD is quoting 5 to 10 percent performance gains over the existing Ryzen 9 9950X3D across creative workloads, with applications like DaVinci Resolve, Blender, and large-scale source code compilations such as Unreal Engine and Chromium cited specifically. Some third-party analyses of AMD’s slide deck suggest gains of up to 13 percent in select tasks, though those figures come with the usual caveats around controlled testing conditions.
It is worth stressing that AMD is not pitching this primarily as a gaming upgrade. The company acknowledges that standard X3D gaming performance is already exceptional, and incremental frame rate gains from the dual-cache design are unlikely to be the headline story. Where AMD says the 9950X3D2 will really distinguish itself is in workloads that live and die by data access latency: large software builds, game engine compiles, AI model training on-device, 3D rendering pipelines, and complex content creation workflows.
That 200W TDP is a number worth paying close attention to, and AMD’s note that a liquid cooler is recommended for optimal performance underscores just how much heat this chip is designed to manage. AMD has historically made strong arguments for the efficiency credentials of its Zen architecture; we have covered that ground in detail at BonTech Labs, including why Intel continues to trail AMD on power efficiency. Whether dual 3D V-Cache pushes AMD’s thermal story in a direction that complicates those comparisons will be worth examining carefully when review hardware is in hand.
The Long Road to Announcement
The 9950X3D2 has had a peculiar path to official existence. Rumours of a dual X3D design circulated throughout 2025, and by the time CES 2026 arrived, most enthusiasts expected AMD to confirm it alongside the Ryzen 7 9850X3D. It did not. The chip was conspicuously absent from AMD’s CES press event, and it remained officially unacknowledged for weeks afterwards.
Then, just days ago, ASRock inadvertently published BIOS support documentation for the 9950X3D2 across its motherboard lineup, effectively announcing the chip before AMD had a chance to. This morning’s video from Jack Huynh brings everything to light at last, with a confirmed worldwide launch date of April 22nd.
For owners of existing AM5 motherboards, the transition should be straightforward. The 9950X3D2 supports the same chipset lineup as current Ryzen 9000 series processors, including X870E, X870, B650E, B650, and A620, so a BIOS update should be all that is required.
What About Zen 6?
The 9950X3D2 arrives at an interesting moment on AMD’s roadmap. Zen 5 has proven competitive across both consumer and professional segments, but speculation about what comes next is already building. If you are trying to decide whether now is the right time to invest in an AM5 flagship or whether it is worth waiting, BonTech Labs has a detailed breakdown of what Zen 6 and AVX-512 support means for PC and server buyers, and it is worth reading before committing to a platform decision.
Pricing and Availability
AMD has not yet revealed the retail price, and that remains the most consequential unknown right now. The Ryzen 9 9950X3D currently sits at around $675 to $700 in most markets. The 9950X3D2 carries additional manufacturing complexity with its three-die package design, so a premium over the existing flagship is virtually certain. Whether AMD prices it to compete with its own Threadripper line or positions it closer to the top of the mainstream desktop stack will define its appeal to the professional and enthusiast markets it is clearly targeting.
We will be pursuing review hardware ahead of the April 22nd launch and will have full performance analysis live as close to release as possible.
GAMDIAS has introduced the ATLAS M5 series, a new line of mid‑tower PC cases designed to offer wider component visibility and improved airflow. The range includes two models, the ATLAS M5 and the ATLAS M5 CG, with the latter being distinguished by a single-piece curved tempered glass panel.
Both cases focus on panoramic component presentation. The ATLAS M5 CG uses an L‑shaped curved glass panel for an unobstructed view of the interior, while the standard ATLAS M5 features tempered glass panels on the front and side. The design removes corner obstructions to create a cleaner showcase layout.
Cooling is handled by three pre‑installed NOTUS M1 ARGB PWM fans, with support for up to nine fans in total. The cases also include an integrated ARGB light strip and offer multiple radiator mounting points for liquid cooling setups.
Connectivity is provided through a side‑mounted I/O panel with a USB 3.2 Gen2x2 Type‑C port, two USB 3.0 ports, LED controls and HD audio. Inside, the ATLAS M5 supports Mini‑ITX, Micro‑ATX and ATX motherboards, GPUs up to 425mm long and PSUs up to 140mm. Storage options include configurations for 3.5‑inch and 2.5‑inch drives. To keep your system clean and simplify maintenance, dust filters are included at the top, side and bottom of the case.
The ATLAS M5 will be available around $84.90, while the Atlas M5 CG will cost slightly more at $99.90.
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Apple has officially announced the M5 Pro and M5 Max, the new chips powering the latest 14-inch and 16-inch MacBook Pro, with pre-orders opening March 4 and availability from March 11. On the surface, this looks like another generational chip update, but dig into what Apple has actually done here, and it is a more interesting story than the spec sheet alone suggests.
A New Architecture at the Core of It
The biggest change with M5 Pro and M5 Max is not the core count or the clock speeds; it is how Apple has built the chips in the first place. Both are constructed using what Apple calls Fusion Architecture, which bonds two third-generation 3nm dies together into a single package using TSMC’s advanced SoIC packaging technology. Every M1 through M4 Pro and Max before this was a single monolithic die. That changes here, and the reason why matters.
TSMC’s manufacturing process limits how large a single die can be while maintaining reasonable yield. By splitting the design across two smaller dies and bonding them together, Apple sidesteps that constraint and can reach memory bandwidth and core count figures that a single N3P die could not have delivered economically. The key claim Apple is making is that the inter-die interconnect is fast and low-latency enough that the operating system and applications treat the package as a single unified device, preserving the unified memory model that Apple Silicon has always depended on. Apple has done something similar at the Ultra tier since the M1 Ultra in 2022, but bringing it to the Pro and Max tiers for laptop chips is a harder engineering challenge, and apparently one Apple has now solved.
Apple M5 Pro and M5 Max CPU’s: More Cores, New Core Design
M5 Pro and M5 Max both run an 18-core CPU comprising six super cores and twelve all-new performance cores. The super core is Apple’s highest-performance core design, the same one introduced in the base M5, and Apple claims it delivers the world’s fastest single-threaded performance, driven by increased front-end bandwidth, a revised cache hierarchy, and better branch prediction.
The twelve performance cores are a new design built specifically for the Pro and Max tiers and are not the same as the efficiency cores in previous generations. Where M4 Pro’s E-cores were optimised primarily for power gating, the new performance cores in M5 Pro and M5 Max are designed to deliver sustained multithreaded throughput at lower power than the super cores. That distinction is important for professionals running long compilation jobs, simulations, and rendering workloads that sit somewhere between light background tasks and all-out burst workloads.
Apple is claiming a 30 percent multithreaded uplift for M5 Pro over M4 Pro, which is the largest single-generation CPU gain at the Pro tier since the original M1 Pro. M4 Pro had 14 cores and M5 Pro jumps to 18, a 29 percent increase in core count alone, so the claim is internally consistent. M5 Max gets a more modest 15 percent MT uplift over M4 Max, reflecting the smaller core count jump from 16 to 18.
GPU and Neural Accelerators
M5 Pro gets up to a 20-core GP, U and M5 Max scales to 40 cores. The M5 Pro GPU core count matches the M4 Pro exactly, so the graphics performance gains here are entirely from architectural improvements per core rather than from adding more cores. Apple puts that at around 20 percent better conventional graphics performance and up to 35 percent for ray-traced workloads, with the ray-tracing improvement specifically attributed to Apple’s third-generation ray-tracing engine alongside second-generation dynamic caching and hardware-accelerated mesh shading support.
The more significant GPU addition is the Neural Accelerator that sits inside each GPU core. This is separate from the Neural Engine that handles background Apple Intelligence and Core ML workloads. The Neural Accelerators are dedicated to accelerating matrix multiplication operations that dominate large-model inference when they run through the GPU compute pipeline, as they do in applications like LM Studio and ComfyUI. Apple claims over 4x the peak GPU compute for AI relative to M4 Pro and M4 Max. However, it is worth noting that this figure reflects the Neural Accelerator path specifically, not the conventional shader performance improvement, which is the more measured 20 percent figure.
Memory Bandwidth: The Number That Actually Matters
M5 Pro supports up to 64 GB of unified memory with 307 GB/s of bandwidth, up from 48 GB and 273 GB/s on M4 Pro. M5 Max holds at a maximum capacity of 128 GB but raises bandwidth from 546 GB/s to 614 GB/s in the top 40-core configuration.
For a growing number of professional workloads, memory bandwidth is more important than raw compute performance, and local LLM inference is the clearest example of why. When generating tokens, a large language model must load its full parameter weights from memory on every forward pass. For a 70B-parameter model in 16-bit floating point, that is roughly 140 GB of data moving per token generated, with comparatively little computation performed on it. That makes the workload bandwidth-bound rather than compute-bound, which means 614 GB/s translates directly into faster token generation. For context, AMD’s Ryzen AI Max Plus in the best Windows laptop configuration delivers around 273 GB/s, less than M5 Pro and considerably less than M5 Max. M5 Max also has the memory capacity to run models that cannot fit on any discrete GPU configuration available today, making the bandwidth advantage meaningful in practice rather than just on paper.
Everything Else Worth Knowing About Apple’s new M5 Pro and M5 Max SoCs
Thunderbolt 5 is standard across M5 Pro and M5 Max, and Apple specifies that each port has its own dedicated on-chip controller rather than sharing bandwidth through a motherboard switch. That means each port gets the full 120 Gb/s bandwidth independently. The Media Engine handles H.264, HEVC, and AV1 decode, and ProRes encode and decode, with the Max tier doubling the encode and ProRes throughput, as it has in previous generations. Internal SSD speeds are claimed at up to 14.5 GB/s, roughly double the previous generation, which matters for model loading and high-bitrate video workflows. The new MacBook Pro also picks up Apple’s N1 wireless chip, bringing Wi-Fi 7 and Bluetooth 6.
One feature that tends to get overlooked in launch coverage is Memory Integrity Enforcement, which Apple’s platform security documentation confirms is available on M5-class processors. It is an always-on, hardware-level memory safety mechanism that does not compromise device performance and is specifically designed to protect the kernel attack surface. For enterprise and research users, that is a meaningful security addition that no competing laptop platform currently matches.
The Competitive Picture
No Windows laptop in 2026 combines the memory bandwidth, memory capacity, and power efficiency of M5 Max in a laptop form factor. AMD Strix Halo is the closest competitor for the LLM inference use case and deserves credit for meaningfully closing the gap over recent generations. Still, the bandwidth gap remains a structural disadvantage to overcome within laptop thermal and form-factor constraints. Qualcomm’s Snapdragon X2 Elite is a credible CPU competitor at the consumer tier. Still, the GPU and memory bandwidth situation is not on the same level at the Pro and Max tiers.
Wrapping it Up: Apple M5 Pro and M5 Max look the part on paper
M5 Pro and M5 Max are genuine steps forward,d not just tick-tock updates. Fusion Architecture is the most important Apple Silicon architectural change since M1 Ultra, now applied to the chips that actually go into MacBook Pros. The memory bandwidth figures are the highest available in any laptop, the CPU gains at the Pro tier are the strongest in years, and the Neural Accelerator addition positions both chips well for the continued growth of local AI inference as a professional workload.
Whether Apple’s claimed numbers hold up in independent testing is the question that matters most right now, and that answer starts arriving when hardware ships on March 11.
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