We saw an Intel Xeon 6 SoC-based next-generation SmartNIC DPU at Computex 2026. This Senao SX906 is really neat
The post This is an Intel Xeon 6 SoC DPU on a PCIe Card from Senao at Computex 2026 appeared first on ServeTheHome.
Vendors have been quick to adopt the latest NVIDIA RTX Spark SoC in their devices, and MSI has deployed it in both mini PCs and laptops. MSI Power EdgeMesa N AI+ Mini PC and Prestige Flip AI+ Laptop With NVIDIA RTX Spark, Delivering a Powerful Arm+Blackwell Combo for Strong Compute and AI Performance With the introduction of the "New era of PC" by NVIDIA, its partners are quickly adopting its recently developed RTX Spark SoC, which brings 20 Arm-based CPU cores coupled with 6144 CUDA Cores based on the Blackwell architecture. The SoC is a powerful chip that brings 128 […]
Read full article at https://wccftech.com/msi-launches-edgemesa-n-ai-min-pc-and-prestige-flip-ai-laptop/
In our Supermicro SYS-112D-36C-FN3P review, we see how this 36 core Intel Xeon 6 SoC edge server with 2x 100GbE onboard performs
The post Supermicro SYS-112D-36C-FN3P Review A 36 Core Intel Xeon 6 SoC Server with 2x 100GbE appeared first on ServeTheHome.
In our Supermicro SYS-112D-40C-FN8P review, we see how this system leverages the Intel Xeon 6 SoC (Granite Rapids-D) to provide 8x 25GbE
The post Supermicro SYS-112D-40C-FN8P Review A 40 Core Intel Xeon 6 SoC Server with 8x 25GbE appeared first on ServeTheHome.
Nvidia CEO Jensen Huang is reportedly preparing to shake up the mobile computing market at Computex in June. It is claimed that Nvidia will be launching new Arm-based processors for laptops, including the N1 and N1X.
Reports from CTEE (via VideoCardz) indicate that Nvidia has booked substantial space at the Taipei International Convention Center for the first week of June. This aggressive scheduling aligns with recent leaks of a “GB10-derived” consumer SoC, the result of a high-profile partnership with MediaTek.
While Qualcomm has spent the last two years attempting to legitimise the Windows-on-Arm (WoA) platform with the Snapdragon X Elite, Nvidia is reportedly aiming for a “day-one” advantage by leveraging its dominance in graphics and AI.
The N1X is tipped to be the flagship of this new family, reportedly featuring a 20-core Arm CPU paired with a Blackwell-based iGPU. Meanwhile, the standard N1 silicon is expected to target mainstream efficiency, bringing AI inference capabilities to everyday productivity laptops.
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KitGuru says: The N1X should have plenty of GPU power for gaming, assuming current rumours are accurate, so we'll be particularly keen to see that chip in action.
The post Nvidia will reportedly showcase N1 SoC for laptops at Computex 2026 first appeared on KitGuru.
New LLVM patches confirm additional RDNA 4m variants alongside GFX1170 with similar instruction capabilities. AMD Quietly Expands Next-Gen iGPU Roadmap by Adding New RDNA 4m Graphics Targets, GFX1171 and GFX1172 Earlier compiler patches showed that RDNA 4m incorporates several RDNA 4-style instruction-set upgrades, such as support for FP8 and BF8 data formats, along with WMMA matrix instructions used in AI workloads. Now, AMD is further expanding its next-gen integrated GPU roadmap, as new Linux compiler patches unveil two additional RDNA 4m graphics targets. These are the GFX1171 and GFX1172. These targets are now joining the recently discovered GFX1170, confirming that […]
Read full article at https://wccftech.com/amd-adds-rdna-4m-gpu-targets-gfx1171-and-gfx1172-hinting-at-next-gen-zen-6-apu-graphics/
Weirdly, the latest open-world title developed by Pearl Abyss doesn't even run on Intel GPUs. Crimson Desert Developer, Pearl Abyss, Confirms The Game Does Not Support Intel Arc GPUs; No Indication of Future Support Either [Update - 3/21/2026] - Intel has offered a statement on the lack of Arc GPU support in Crimson Desert: "We’re aware that Crimson Desert currently doesn’t launch on systems with Intel GPUs and we’re hugely disappointed that players using Intel graphics hardware can’t jump into the world of Pywel at launch. Getting games running smoothly is always a partnership between developers and hardware makers. Over the […]
Read full article at https://wccftech.com/crimson-desert-doesnt-run-on-intel-arc-confirms-pearl-abyss/
Rambus has announced the development of its fastest HBM controller yet, based on the HBM4E standard, offering up to 16 Gbps transfer speeds per pin. Ready For Next-Gen AI Data Center Superchips, Rambus Intros HBM4E Memory Controller As expected, Rambus has developed the world's fastest HBM4E memory controller, offering a 60% boost over its HBM4 controller with up to 16 Gbps pin speeds (vs 10 Gbps on HBM4) and up to 4.1 TB/s of total bandwidth per module (vs 2.56 GB/s on HBM4). The HBM4E standard will be utilized by NVIDIA's Rubin Ultra GPUs and AMD's MI500 series accelerators. Press […]
Read full article at https://wccftech.com/rambus-hbm4e-memory-controller-60-percent-faster-vs-hbm4-at-4-1-tbps/
Apple has officially announced the M5 Pro and M5 Max, the new chips powering the latest 14-inch and 16-inch MacBook Pro, with pre-orders opening March 4 and availability from March 11. On the surface, this looks like another generational chip update, but dig into what Apple has actually done here, and it is a more interesting story than the spec sheet alone suggests.
The biggest change with M5 Pro and M5 Max is not the core count or the clock speeds; it is how Apple has built the chips in the first place. Both are constructed using what Apple calls Fusion Architecture, which bonds two third-generation 3nm dies together into a single package using TSMC’s advanced SoIC packaging technology. Every M1 through M4 Pro and Max before this was a single monolithic die. That changes here, and the reason why matters.
TSMC’s manufacturing process limits how large a single die can be while maintaining reasonable yield. By splitting the design across two smaller dies and bonding them together, Apple sidesteps that constraint and can reach memory bandwidth and core count figures that a single N3P die could not have delivered economically. The key claim Apple is making is that the inter-die interconnect is fast and low-latency enough that the operating system and applications treat the package as a single unified device, preserving the unified memory model that Apple Silicon has always depended on. Apple has done something similar at the Ultra tier since the M1 Ultra in 2022, but bringing it to the Pro and Max tiers for laptop chips is a harder engineering challenge, and apparently one Apple has now solved.
M5 Pro and M5 Max both run an 18-core CPU comprising six super cores and twelve all-new performance cores. The super core is Apple’s highest-performance core design, the same one introduced in the base M5, and Apple claims it delivers the world’s fastest single-threaded performance, driven by increased front-end bandwidth, a revised cache hierarchy, and better branch prediction.
The twelve performance cores are a new design built specifically for the Pro and Max tiers and are not the same as the efficiency cores in previous generations. Where M4 Pro’s E-cores were optimised primarily for power gating, the new performance cores in M5 Pro and M5 Max are designed to deliver sustained multithreaded throughput at lower power than the super cores. That distinction is important for professionals running long compilation jobs, simulations, and rendering workloads that sit somewhere between light background tasks and all-out burst workloads.
Apple is claiming a 30 percent multithreaded uplift for M5 Pro over M4 Pro, which is the largest single-generation CPU gain at the Pro tier since the original M1 Pro. M4 Pro had 14 cores and M5 Pro jumps to 18, a 29 percent increase in core count alone, so the claim is internally consistent. M5 Max gets a more modest 15 percent MT uplift over M4 Max, reflecting the smaller core count jump from 16 to 18.
M5 Pro gets up to a 20-core GP, U and M5 Max scales to 40 cores. The M5 Pro GPU core count matches the M4 Pro exactly, so the graphics performance gains here are entirely from architectural improvements per core rather than from adding more cores. Apple puts that at around 20 percent better conventional graphics performance and up to 35 percent for ray-traced workloads, with the ray-tracing improvement specifically attributed to Apple’s third-generation ray-tracing engine alongside second-generation dynamic caching and hardware-accelerated mesh shading support.
The more significant GPU addition is the Neural Accelerator that sits inside each GPU core. This is separate from the Neural Engine that handles background Apple Intelligence and Core ML workloads. The Neural Accelerators are dedicated to accelerating matrix multiplication operations that dominate large-model inference when they run through the GPU compute pipeline, as they do in applications like LM Studio and ComfyUI. Apple claims over 4x the peak GPU compute for AI relative to M4 Pro and M4 Max. However, it is worth noting that this figure reflects the Neural Accelerator path specifically, not the conventional shader performance improvement, which is the more measured 20 percent figure.
M5 Pro supports up to 64 GB of unified memory with 307 GB/s of bandwidth, up from 48 GB and 273 GB/s on M4 Pro. M5 Max holds at a maximum capacity of 128 GB but raises bandwidth from 546 GB/s to 614 GB/s in the top 40-core configuration.
For a growing number of professional workloads, memory bandwidth is more important than raw compute performance, and local LLM inference is the clearest example of why. When generating tokens, a large language model must load its full parameter weights from memory on every forward pass. For a 70B-parameter model in 16-bit floating point, that is roughly 140 GB of data moving per token generated, with comparatively little computation performed on it. That makes the workload bandwidth-bound rather than compute-bound, which means 614 GB/s translates directly into faster token generation. For context, AMD’s Ryzen AI Max Plus in the best Windows laptop configuration delivers around 273 GB/s, less than M5 Pro and considerably less than M5 Max. M5 Max also has the memory capacity to run models that cannot fit on any discrete GPU configuration available today, making the bandwidth advantage meaningful in practice rather than just on paper.
Thunderbolt 5 is standard across M5 Pro and M5 Max, and Apple specifies that each port has its own dedicated on-chip controller rather than sharing bandwidth through a motherboard switch. That means each port gets the full 120 Gb/s bandwidth independently. The Media Engine handles H.264, HEVC, and AV1 decode, and ProRes encode and decode, with the Max tier doubling the encode and ProRes throughput, as it has in previous generations. Internal SSD speeds are claimed at up to 14.5 GB/s, roughly double the previous generation, which matters for model loading and high-bitrate video workflows. The new MacBook Pro also picks up Apple’s N1 wireless chip, bringing Wi-Fi 7 and Bluetooth 6.
One feature that tends to get overlooked in launch coverage is Memory Integrity Enforcement, which Apple’s platform security documentation confirms is available on M5-class processors. It is an always-on, hardware-level memory safety mechanism that does not compromise device performance and is specifically designed to protect the kernel attack surface. For enterprise and research users, that is a meaningful security addition that no competing laptop platform currently matches.
No Windows laptop in 2026 combines the memory bandwidth, memory capacity, and power efficiency of M5 Max in a laptop form factor. AMD Strix Halo is the closest competitor for the LLM inference use case and deserves credit for meaningfully closing the gap over recent generations. Still, the bandwidth gap remains a structural disadvantage to overcome within laptop thermal and form-factor constraints. Qualcomm’s Snapdragon X2 Elite is a credible CPU competitor at the consumer tier. Still, the GPU and memory bandwidth situation is not on the same level at the Pro and Max tiers.
M5 Pro and M5 Max are genuine steps forward,d not just tick-tock updates. Fusion Architecture is the most important Apple Silicon architectural change since M1 Ultra, now applied to the chips that actually go into MacBook Pros. The memory bandwidth figures are the highest available in any laptop, the CPU gains at the Pro tier are the strongest in years, and the Neural Accelerator addition positions both chips well for the continued growth of local AI inference as a professional workload.
Whether Apple’s claimed numbers hold up in independent testing is the question that matters most right now, and that answer starts arriving when hardware ships on March 11.
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