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SK Hynix Unpacks Advanced Packaging Technologies, Including Intel EMIB, For Its Next-Gen HBM Memory As It Eyes 3D Structures For The Future

23 August 2026 at 20:30

A slide titled 'Advanced PKG Future Direction' illustrates three structures: '2D Structure' with 'PKG to PKG on Board,' '2.5D Structure' with 'Die to Die on Interposer,' and '3D Structure' with 'Die on Die,' each depicted with different chip designs and connections.

SK Hynix is leveraging advanced packaging technologies such as Intel's EMIB for its next-gen HBM solutions, which will eventually enter the 3D packaging stage. Scaling HBM Comes With Big Challenges & SK Hynix Is Leveraging Advanced Packaging Solutions To Address Them As It Ventures Into The 3D Era At Hot Chips 2026, Jaesik Lee (VP Package Engineering at SK Hynix) presented the "Advanced Packaging for High-Bandwidth Memory" brief, which talks about how the company plans to leverage advanced packaging tech to accelerate its HBM roadmap. The company started by presenting how HBM is currently built. The HBM structure consists of […]

Read full article at https://wccftech.com/sk-hynix-advanced-packaging-technologies-intel-emib-next-gen-hbm-memory/

AMD’s EPYC Venice Becomes Industry’s First 2nm HPC CPU To Achieve Volume Ramp As It Races Towards Agentic AI Leadership

21 May 2026 at 14:25

AMD's EPYC Venice Becomes Industry's First 2nm HPC CPU To Achieve Volume Ramp As It Races Towards Agentic AI Leadership

AMD's EPYC Venice CPUs have entered volume production, making them the first HPC product to achieve the milestone on TSMC's 2nm process tech. AMD & TSMC Enter Volume Production On The Industry's First 2nm HPC Chip, 6th Gen EPYC Venice The Agentic AI boom is driving the CPU market up, unlike anything that came before. High-Performance CPUs are seeing massive demands, and AMD, being a leader in HPC, has just achieved volume ramp of its next-generation EPYC Venice CPUs based on the Zen 6 core architecture. The volume ramp was achieved on TSMC's cutting-edge 2nm process technology. Looking ahead, AMD […]

Read full article at https://wccftech.com/amd-epyc-venice-industrys-first-tsmc-2nm-hpc-chip-to-achieve-volume-ramp/

NVIDIA Rubin & Rubin Ultra Platforms Facing Design/Spec Issues As Per Rumors While AMD MI500 Positioned For 2H 2027 Launch

9 May 2026 at 14:00

An individual in a leather jacket is presenting a large circuit board design next to a stack of horizontal units.

NVIDIA's Rubin platforms are rumoredly facing design/spec issues, making way for the competition, such as AMD MI500, to get the headstart with HBM4E in 2027. Will AMD Beat NVIDIA In The Race To HBM4E? Design & Spec Changes In Rubin Platforms Can Give MI500 The Lead Based on recent reports, NVIDIA's upcoming Rubin and Rubin Ultra platforms are undergoing serious design and spec changes. These changes come ahead of the expected launch of the Rubin generation, which is going to uplift AI performance miles above Blackwell with new features, efficiency upgrades & brand new architectures. As per the rumors, NVIDIA […]

Read full article at https://wccftech.com/nvidia-rubin-rubin-ultra-platforms-facing-design-spec-issues-amd-mi500-positioned-for-2h-2027/

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