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SK Hynix Unpacks Advanced Packaging Technologies, Including Intel EMIB, For Its Next-Gen HBM Memory As It Eyes 3D Structures For The Future

23 August 2026 at 20:30

A slide titled 'Advanced PKG Future Direction' illustrates three structures: '2D Structure' with 'PKG to PKG on Board,' '2.5D Structure' with 'Die to Die on Interposer,' and '3D Structure' with 'Die on Die,' each depicted with different chip designs and connections.

SK Hynix is leveraging advanced packaging technologies such as Intel's EMIB for its next-gen HBM solutions, which will eventually enter the 3D packaging stage. Scaling HBM Comes With Big Challenges & SK Hynix Is Leveraging Advanced Packaging Solutions To Address Them As It Ventures Into The 3D Era At Hot Chips 2026, Jaesik Lee (VP Package Engineering at SK Hynix) presented the "Advanced Packaging for High-Bandwidth Memory" brief, which talks about how the company plans to leverage advanced packaging tech to accelerate its HBM roadmap. The company started by presenting how HBM is currently built. The HBM structure consists of […]

Read full article at https://wccftech.com/sk-hynix-advanced-packaging-technologies-intel-emib-next-gen-hbm-memory/

Samsung Leverages Advanced Logic Processes To Advance HBM As It Works On Its Next-Gen zHBM DRAM That 3D Stacks Memory On Compute

23 August 2026 at 18:45

A close-up of a Samsung-branded sheet covered with numerous small, gold-colored semiconductor chips.

Samsung presents a bold vision for evolving the HBM base die with advanced logic processes that reviews the architecture’s bandwidth and power challenges, then outlines a three-phase roadmap, from area reclamation and functional expansion to full 3D ZHBM integration, that transforms the base die into an intelligent partner for next-generation AI systems. Samsung Charts Three-Phase HBM Roadmap Toward True 3D ZHBM That Stacks DRAM Directly On Compute For AI In the presentation by Sangwook Han, who is part of Samsung's DRAM Design Team, the main discussion revolves around the evolution of HBM using advanced logic processes, with the HBM base […]

Read full article at https://wccftech.com/samsung-leverages-advanced-logic-processes-to-advance-hbm-works-on-3d-stacked-zhbm/

Qualcomm’s HBC Stacks Compute Beneath DRAM To Smash The AI Memory Wall, Claiming 6x The Bandwidth Per Watt Of HBM

24 June 2026 at 21:15

A layered chip with gold-colored elements is shown above the text '200x capacity per watt vs. SRAM*'.

Qualcomm is unveiling its breakthrough for the AI data center market called HBC (High-Bandwidth Compute), to break the memory wall. Qualcomm's HBC Is A Memory Accelerator That Is Stacked Under DRAM, Offering A Major Boost Versus Standard SRAM & HBM Configurations At its Investors Day 2026, Qualcomm unveiled HBC under its Dragonfly brand, an innovative technology that aims to offer a major boost in memory capacity and bandwidth. The HBC architecture deploys a purpose-built & near-memory solution that bonds compute with boosted memory bandwidth in a 3D stacked chip design. With this, Qualcomm aims to solve the memory bottlenecks that […]

Read full article at https://wccftech.com/qualcomm-hbc-stacks-compute-beneath-dram-to-smash-the-ai-memory-wall/

SanDisk Bets on Stacking NAND and Compute on One Chip as HBM Shortages Choke the AI Boom

21 June 2026 at 23:45

HBF Memory Offers Higher Capacities Than HBM But NVIDIA Isn't Interested In It (Yet), Sampling This Year With Google A Key-Customer 1

SanDisk is looking for more innovative solutions to address memory limitations, such as stacking NAND Flash within chips. Memory Limitations Push DRAM/NAND Maker To Get More Innovative, SanDisk Proposes The Stacking of NAND Flash Within Chips The rapid rise of AI & the proportional demand for compute has led to the exposure of bottlenecks, which are pushing DRAM and NAND manufacturers into going with the out-of-the-box approach. In the past, chipmakers called it a day by introducing new memory technologies, and DRAM was the primary component. But the rise in costs, development/yield drawbacks, & increased power have led to a […]

Read full article at https://wccftech.com/sandisk-bets-on-stacking-nand-and-compute-on-one-chip/

Micron Doubles Down on AI Memory With 256 GB DDR5 RDIMMs Hitting 9200 MT/s, a 40% Leap Over Today’s Modules

12 May 2026 at 17:35

Micron Doubles Down on AI Memory With 256 GB DDR5 RDIMMs Hitting 9200 MT/s, a 40% Leap Over Today's Modules

Micron has started to ship its fastest DDR5 RDIMM memory modules, which feature 256 GB capacities & up to 9200 MT/s speeds. Micron Offers 40% Boost Vs Current "In-Volume" DDR5 RDIMM Memory Modules, Brings 256 GB Capacities With 9200 MT/s Speeds As Agentic AI requirements grow, memory makers are rolling out faster and higher-capacity memory kits to meet the demands of AI firms. JEDEC is also pushing the DDR5 MRDIMM standard up to 12,800 MT/s, and today, Micron has announced that it is sampling its 256 GB DDR5 RDIMM modules with up to 9200 MT/s speeds. The main highlights include: […]

Read full article at https://wccftech.com/micron-doubles-down-on-ai-memory-256-gb-ddr5-rdimms-hitting-9200-mtps/

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