How do you cool a giant rack of AI hardware? With an even bigger heat exchanger. Delta's GoCool-150 is a liquid-to-air CDU that is designed to dissipate 150kW of heat from NVL72 and other high-density liquid cooled racks
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Giga Computing, a GIGABYTE subsidiary, has announced support for AMD’s 6th Gen EPYC server processors across its server portfolio. The company also introduced its first system based on the AMD EPYC 9006 platform at AMD Advancing AI 2026 in San Francisco.
AMD’s 6th Gen EPYC platform introduces two-socket options designed to address different data center deployment models. The SP7 platform targets performance-sensitive infrastructure with higher memory bandwidth, PCIe Gen6 connectivity, and support for up to 256 cores and 512 threads per socket. The SP8 platform focuses on scalable, power-conscious deployments for virtualization, databases, and edge workloads.
Both socket platforms support AMD’s “Zen 6” and density-oriented “Zen 6c” core designs. This gives system builders flexibility to prioritize per-core performance or core density depending on the workload.
The EPYC 9006 SP7 platform supports 16-channel DDR5 memory and PCIe Gen6, positioning it for GPU-dense AI infrastructure, HPC, hyperscale cloud, and telecommunications workloads. The increased core count and I/O capacity are designed to support high VM density, data-intensive services, and CPU orchestration workloads that feed large GPU clusters.
Giga Computing stated that SP7-based systems could scale beyond 40,000 CPU cores in a single liquid-cooled rack configuration. Such designs would be targeted at large AI deployments where CPUs handle data preparation, pipeline orchestration, storage and network services, and concurrent agent workflows alongside accelerators.
New SP7 systems include the R165-DG2-CS1, a 1U single-socket rack server with closed-loop liquid cooling that supports processors with up to 256 cores at maximum power. Giga Computing also highlighted the B685-D80-LS1, a 6U, ten-node blade server with direct liquid cooling for high-density HPC environments.
The SP8 platform is aimed at deployments that prioritize performance per watt, space efficiency, and consistent scale-out operation. AMD EPYC 9006 SP8 processors support up to 128 PCIe Gen6 lanes and two DIMMs per memory channel, providing substantial I/O and memory expansion in a smaller platform footprint.
Giga Computing is positioning SP8 systems for virtualization, database, enterprise infrastructure, and edge deployments where power and rack constraints can be as important as absolute compute density. The platform is intended to offer a lower-footprint alternative to larger EPYC configurations while retaining current-generation PCIe and DDR5 capabilities.
According to Giga Computing, systems based on AMD EPYC 9006 SP7 processors are expected to begin shipping alongside AMD’s November 2026 launch. SP8-based systems are scheduled to follow in March 2027.
Separately, GIGABYTE TECHNOLOGY announced expanded support for DDR5 modules based on CXMT memory chips across its AMD and Intel desktop motherboard platforms. The update is intended to broaden memory sourcing options during ongoing DDR5 supply constraints.
GIGABYTE’s AMD AM5 800- and 600-series motherboards now support CXMT-based 16Gb and 24Gb DDR5 DIMMs through updated BIOS releases. The company stated that, following AMD AGESA 1.3.0.1c support and GIGABYTE memory optimization work, compatible systems can operate CXMT-based modules at speeds up to 8200 MT/s.
Intel 800- and 700-series motherboard platforms already support CXMT DDR5 memory using current BIOS releases, according to GIGABYTE. No additional update is required for those platforms.
The new compatibility gives system builders another qualified DDR5 source as memory availability and pricing continue to affect the broader PC component market. Updated BIOS versions for AMD 800- and 600-series boards are available through GIGABYTE’s product support pages.
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ASUS has announced a new server portfolio based on 6th Gen AMD EPYC 9006 processors, built specifically around the efficiency-optimized SP8 socket rather than the 256-core SP7 flagship. The lineup includes dual-socket RS700A and RS720A systems designed for maximum compute density, alongside single-socket RS500A and RS520A systems targeting more space-constrained enterprise deployments.
The new platforms support PCIe Gen6 connectivity, advanced DDR5 memory configurations, and E3.S NVMe storage. ASUS is positioning the systems for enterprise AI inference, virtualization, simulation, cloud infrastructure, and storage-intensive workloads.
The dual-socket RS700A/720A series is the higher-density option in the new portfolio. The systems support 32 DIMM slots and MRDIMM memory configurations, allowing the platform to address workloads requiring substantial memory capacity and bandwidth.
ASUS also specifies support for up to 32 E3.S storage bays in a 2U chassis. Combined with PCIe Gen6, this configuration is aimed at high-throughput environments that require dense NVMe capacity, accelerator connectivity, or large-scale network expansion.
The RS700A/720A systems are intended for AI inference infrastructure, technical computing, complex simulations, and enterprise applications where compute density and memory bandwidth are key design considerations.
The RS500A/520A series uses a single AMD EPYC 9006 processor socket and is designed for mainstream enterprise infrastructure and rack-constrained environments. ASUS specifies a chassis depth of less than 800 mm, which may simplify deployment in locations with limited cabinet depth or edge-oriented infrastructure.
Despite its smaller footprint, the single-socket series retains support for PCIe Gen6 E3.S storage. ASUS also notes shared modular components with the larger RS700A and RS720A platforms, which could simplify platform qualification, service processes, and component inventory for organizations standardizing across both system classes.
ASUS has incorporated its DC-MHS modular architecture into the new systems. The design separates I/O, high-power module, fan, and storage components into distinct chassis zones. This architecture is intended to simplify service access and provide a more modular platform design across server configurations.
The company also includes its DIMM.2 implementation, which places M.2 storage in the DIMM area rather than a conventional motherboard location. ASUS states that this placement uses the airflow available around the memory subsystem to improve M.2 SSD cooling and reduce the risk of thermal throttling without adding dedicated heatsinks.
Thermal Radar 3.0 with PID control provides dynamic fan-speed management. The system adjusts fan behavior in real time based on thermal conditions to balance component cooling requirements against system power consumption and acoustic output.
ASUS also highlighted tool-less serviceability features intended to reduce maintenance time and support faster component replacement. This approach is increasingly relevant in AI and HPC environments, where sustained utilization and infrastructure availability can make scheduling service windows difficult.
ASUS has not published pricing or a firm release date for the RS700A/720A and RS500A/520A series, saying only that the platforms are coming soon.
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Supermicro introduced its new H15 server portfolio, built around 6th Gen AMD EPYC 9006 Series CPUs. These servers are designed to work with AMD Instinct GPUs and AMD Pensando networking solutions. In addition, Supermicro is expanding its AMD GPU offerings with new PCIe GPU servers built for AMD Instinct MI350P GPUs and the previously announced Supermicro AMD Helios rack-scale platform, which incorporates AMD Instinct MI455X GPUs. This announcement includes details about the CPU platform, GPU and networking hardware, and the rack-scale system that integrates these components, targeting agentic AI, cloud, enterprise, and HPC workloads.
The H15 architecture is based on Supermicro’s Data Center Building Block Solutions (DCBBS), which standardizes modular rack-scale deployment across its server range rather than designing each chassis individually. H15 systems support 6th Gen AMD EPYC 9006 Series processors with up to 256 cores and 512 threads per socket, which Supermicro says deliver up to 1.7x the generational performance of the prior lineup while offering more memory and I/O bandwidth. The company’s key message is simple: increased cores and memory bandwidth per socket let users run more AI agents or enterprise workloads per node without surpassing power limits, a critical factor as data center power availability often restricts rack capacity rather than compute density.
Supermicro classifies the H15 lineup into six system categories, each tailored for specific deployment scenarios. The Hyper platform is the flagship dual-socket model, designed for enterprise applications, AI inference, virtualization, and cloud workloads, and features a thermal design capable of supporting top-tier AMD EPYC processors. CloudDC is available in both single- and dual-socket versions and adheres to the Open Compute Project’s Data Center Modular Hardware System (DC-MHS) standard, enabling interoperability with other OCP-compliant data center components rather than restricting users to a Supermicro-specific rack system.
GrandTwin is a high-density 2U, four-node system designed for scale-out workloads like object storage, virtualization, cloud services, and HPC. FlexTwin offers a more compact 1U, two-node, dual-CPU setup with liquid cooling, tailored for cloud-native and hyperscale environments where rack density and power efficiency take precedence over node flexibility. Supermicro’s Petascale Storage series rounds out its non-GPU portfolio with high-capacity all-flash platforms in 1U and 2U form factors, supporting up to 4.8PB per system for AI data lakes, large-scale analytics, and HPC storage. These platforms are built on software-defined storage rather than fixed hardware RAID.
The H15 8U 10-node SuperBlade is the rack-scale blade system in the portfolio, supporting single- and dual-socket blade configurations in air- or liquid-cooled options. It is designed for mixed CPU and GPU deployments used in HPC, AI inference, agentic AI, and enterprise computing, providing high blade density without requiring a full GPU rack.
Supermicro introduced two 5U PCIe GPU servers, the AS-5126GS-TNRT and AS-5126GS-TNRT2, featuring AMD Instinct MI350P PCIe GPUs. Each system can support up to 10 GPUs within a standard 5U air-cooled chassis, maintaining compatibility with data centers that already support such cooling and power configurations and avoiding the need for liquid cooling. The MI350P GPU provides up to 144GB of HBM3e memory and supports low-precision AI numeric formats, making it suitable for both inference and training workloads where memory capacity, rather than raw compute power, is often the limiting factor.
Supermicro’s MI350P systems utilize the AMD Pensando Pollara 400 AI NIC, an open Ethernet networking card designed for AI infrastructure. It manages front-end, storage, and scale-out traffic in MI350P deployments. Since it operates over standard Ethernet rather than a proprietary interconnect, Pollara 400 enables customers to scale their cluster from a single server to multi-rack setups without being locked into a closed networking stack. This flexibility is a key point that Supermicro and AMD highlight as a competitive advantage over interconnect options limited to a single GPU vendor’s ecosystem.
The Supermicro AMD Helios Platform, created in partnership with AMD, is a liquid-cooled, 72-GPU rack system designed around AMD Instinct MI455X GPUs, 6th Gen AMD EPYC processors, AMD Pensando networking, and the AMD ROCm software suite. It targets large-scale AI training and high-throughput inference for organizations working with frontier-scale models and can scale from a single rack to larger multi-rack AI clusters. Helios and the new PCIe GPU servers serve different deployment needs: MI350P PCIe systems for enterprises expanding GPU inference or training within existing air-cooled setups, and Helios for organizations constructing dedicated, liquid-cooled AI clusters on a much larger scale.
Supermicro President and CEO Charles Liang explained that the H15 launch emphasizes building infrastructure tailored for performance, scalability, and efficiency, especially as agentic AI adoption increases. He highlighted the DCBBS architecture as key to achieving high performance while enabling flexible rack-scale deployment. Additionally, he mentioned Supermicro’s global services and U.S.-based supply chain as vital supports for customers deploying and scaling AI infrastructure.
AMD’s senior vice president and general manager of Compute and Enterprise AI, Dan McNamara, emphasized that enterprises scaling agentic AI require infrastructure that provides performance, efficiency, and deployment flexibility. He described how combining AMD’s EPYC CPUs, Instinct GPUs, and Pensando networking with Supermicro’s modular server and rack-scale designs can accelerate AI infrastructure deployment while enhancing resource utilization, energy efficiency, and total cost of ownership.
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Advancing AI 2026 was AMD’s biggest launch event yet, big enough that we split our coverage in two. Our first article covered the Instinct MI455X and the 72-GPU Helios rack; this sister piece covers what could not comfortably fit alongside them: the 6th Gen EPYC server CPUs, codenamed Venice, and the Verano host processor. The CPU deserves its own headline. Venice brings up to 256 cores and 512 threads per socket, 1.6TB/s of memory bandwidth, the first PCIe Gen 6 in a server CPU, and 18× the throughput of the first-generation EPYC from 2017.
Venice is also not a chip. It is a portfolio, a point AMD repeated in every session: one CPU profile does not fit all. The same Zen 6 generation fans out into a density part, an enterprise part, a stacked-cache HPC part, and a low-power LPDDR host. So before the speeds and feeds, let’s look at the lineup.
AMD sorts the modern data center into three server classes, and the portfolio is built to populate all of them. General-purpose CPU servers run the web gateways, caches, application tiers, databases, and storage that everything else leans on. GPU servers need a host CPU that keeps the accelerators fed, a job where single-threaded speed and I/O bandwidth beat core count. The third class is dense CPU servers for the orchestration and tool-execution code that has grown up around AI services; that code is branch-heavy and stall-prone, and it wants threads above all.
The lineup consists of four products, and platforms arrive in waves: Venice SP7 in Q4 2026, Venice SP8 in the first half of 2027, and Venice-X and Verano in the second half. AMD splits the same silicon six ways, and the finer cut maps straight onto the three tiers. General purpose gets Venice SP7, SP8, and Venice-X. The host bucket pairs a high-frequency Venice bin with Verano and its LPDDR memory. Dense compute gets what the deck labels Venice 256c: high core count at low power, built to pack as many threads into a rack as the power budget allows. Verano moonlights too: AMD says select customers will deploy it as a general-purpose processor wherever performance per system watt is the binding constraint.
We get a sneak peek at the SKUs thanks to the footnotes. The 256-core EPYC 9996 leads the stack, the 9956 carries the same cores at 400W, and the 96-core 9686F is the high-frequency host part. Helios has its own version of that host silicon, the EPYC 9G76, in every compute tray.
Before the spec tables, a word about where the big socket lands. Venice SP7 is reserved for AMD’s highest-end, no-compromise performance tier: datacenter, hyperscaler, and HPC compute deployments, where throughput per rack is the deciding factor, with no expense spared. The server vendors are already re-tiering around it. Dell has split its long-established PowerEdge naming schema to make room, and this class of compute now sits in a new 9000 series led by the PowerEdge R9825 and Rack Scale M9825, the flagships with 2 Venice chips in a 3U chassis.
The whole family builds on one platform, and nearly every corner of it is new since Turin.
Start with the cores. Zen 6 comes in two flavors: the compact Zen 6c packs 256 cores and 512 threads into a socket at up to 600W, while the standard core stops at 96 but clocks to 5GHz. AMD claims upwards of 20% more per-core performance than competing parts at matched core counts, and density does not thin the cache: even the 256-core die keeps about 4MB of L3 per core, a full gigabyte on the flagship. AVX-512 handles the tokenizers and the 3-to-8-billion-parameter models that increasingly run on the CPU itself.
Feeding those cores requires a much larger memory system: 16 channels of DDR5 at 8,000MT/s, or MRDIMM at 12,800, good for 1.6TB/s per socket, whereas Turin managed 614GB/s from 12 channels. I/O makes the same jump. Venice is the first server CPU with PCIe Gen 6, 128 lanes of it at 64 GT/s, double the per-lane bandwidth of anything else attaching to accelerators today, and the foundation of the host-node claim we unpack later. CXL 3.1 rides on those lanes for memory expansion, and select two-socket AI host platforms trade inter-socket xGMI width for I/O to reach 160 usable lanes. Two quieter additions move data without burning cores: SDXI offloads memory copies and 30 to 50 cores’ worth of crypto, and Smart Data Cache Injection drops network packets straight into cache instead of routing them through DRAM.
Power management gets three new knobs, and they matter because every rack comparison AMD makes later happens inside a power budget. UPP merges the SoC and DIMM budgets into one, so a memory-bound workload shifts watts to the DIMMs and a compute-bound one pulls them back, which either raises performance inside a fixed budget or frees rack power for more nodes. UBPS caps power at low utilization, trading the usual light-load performance bump for a flat, predictable load line; operators who prefer the bump can switch it off. FAST splits one SoC into two personalities, keeping priority cores at high frequency while background cores run slower, so that latency-critical work sharing a socket with batch jobs doesn’t suffer.
For security, Venice extends a confidential-computing lineage that runs from SEV on EPYC 7002 through encrypted state, secure nested paging, and the Trusted I/O that arrived with Turin. New this generation: an enhanced root of trust with RSA-4K and post-quantum algorithms, physical and side-channel attack mitigations, FIPS 140-3 Level 1 certification, and Device Provenance, an attestable manufacturing history that Venice will be among the first AMD products to carry.
The four parts differ more than the shared name suggests.
| Specification | 9006 SP7 | 9006 SP8 | 9006X SP7 | 9006 LP “Verano” |
|---|---|---|---|---|
| Cores | Up to 256 (512 threads) | 8 to 128 | Up to 96 | Up to 72 |
| Peak frequency | 5.0GHz with 96 cores (HF) | HF options offered | ~5.15GHz | Up to 5.0GHz |
| Memory | 16ch, up to 1.6TB/s | 8ch with 2 DIMMs per channel | 16ch MRDIMM at 12,800 MT/s | 24ch LPDDR5X, SOCAMM2 |
| L3 cache | Up to 1024MB | Core-count dependent | 1152MB (3D V-Cache) | Core-count dependent |
| I/O | PCIe Gen 6, 128 lanes 1P | 128 PCIe lanes, 1P and 2P | PCIe Gen 6 | Enhanced xGMI at 112 GT/s |
| Aimed at | Hyperscale density, AI host | Enterprise, edge, NEBS-friendly | HPC, AI pre-processing | Rack-scale AI host |
SP7 is the flagship socket and the one in production now; partner platforms follow in Q4. Its high-frequency bins succeed the Turin HF parts AMD says were among its fastest-ramping SKUs, and their biggest deployment is Helios, where the host CPU in every compute tray joins the rack’s coherent memory domain over Infinity Fabric with 1TB of DDR5 behind it. Because the socket is standard, any SP7 SKU up to the 256-core flagship drops in, a point we covered in the sister article.
SP8 trades the giant socket for system economics. It spans 8 to 128 cores, runs 8 memory channels with 2 DIMMs per channel, maintains 128 PCIe lanes, and comes in 1P and 2P with high-frequency and NEBS-friendly options for telco and edge deployments. AMD’s pitch is right-sized performance for the enterprise, where the metric that wins deals is performance per system dollar rather than per rack.
Venice-X stacks 3D V-Cache on the 96-core high-frequency configuration and takes L3 to 1152MB, roughly 3× the cache per core of the standard SP7 parts. Clocks reach about 5.15GHz, and the full 16-channel, 12,800 MT/s memory system carries over. The targets are simulation and modeling, large-scale analytics, in-memory databases, and AI pre-processing that feeds training pipelines—workloads where a working set held in cache matters more than extra cores.
Verano is the most focused part in the family: an AI host node first, with up to 72 cores at 5GHz, 24 channels of LPDDR5X, and an enhanced 112 GT/s xGMI link for CPU-to-GPU traffic. The LPDDR sits on SOCAMM2 modules that can be replaced in the field, which matters in a fleet where a soldered-down memory failure would otherwise scrap a whole board. It is also AMD’s direct answer to NVIDIA’s Vera, a matchup we will come back to, because AMD certainly did.
AMD made its case in two passes, leading with Turin to show the lead it already holds, then Venice to show how far it is pulling away.
AMD aimed most of its comparisons at NVIDIA’s Vera, the Arm CPU in the Vera Rubin platform, and it opened with the generation it already ships. According to AMD’s rack-level modeling, a rack of Turin delivers 2.4× Vera’s general-purpose throughput and twice the agents per watt. The model fixes both racks at a 100kW power budget, matches a 2P EPYC 9965 with 384 cores against a 2P Vera board with 176, and averages the results across six workloads: estimated SPECrate 2017, server-side Java, NGINX, Redis, Memcached, and a TPC-C derivative.
Two caveats apply here and to the rest of this article. Vera has not shipped, so every Vera figure is an AMD estimate of the 88-core, 450W part NVIDIA has described in its public materials. And because no standard benchmark exists for agentic workloads, AMD counts hardware threads as a proxy for agents in its agents-per-watt math.
The Intel comparison rests on firmer ground, since both sides are shipping parts that AMD could benchmark directly. Turin’s host CPUs reach 5.0GHz, while the comparable Xeon tops out at 3.9GHz, a 28% frequency advantage that matters when single threads feed GPUs. Socket-for-socket against the 128-core Xeon 6980P, AMD measures Turin at up to 1.4X on SPEC CPU, 1.4X on enterprise Java, 1.8X on HPC, and 1.7X on CPU-based AI.
Venice extends each of those leads. Under the same 100kW rack model, now with 512 Venice cores against Vera’s 176, AMD claims 3.3X Vera’s general-purpose performance. Venice achieves 2.8× the agents per watt of the 136-core Arm AGI, and 1.8× the tokens per second on frontier models when Venice hosts GPUs. That 1.8× figure measures a narrower scenario than the headline suggests, and we return to it in the host-node section below.
On SPECrate 2026, AMD estimates a 2P Venice 9996 at 2070 against 925 for Vera, a 2.2X throughput advantage, and puts the 96-core high-frequency part about 1.2× ahead of Vera per core. Both results were compiled with GCC 15.2, the same toolchain NVIDIA used for its published Vera numbers.
The per-core claim actually grew during launch week. Ravi Kuppuswamy, who runs AMD’s CPU engineering, told the press that AMD had originally claimed a 10% per-core advantage. After NVIDIA published its own Vera numbers earlier in the week, its team reran the comparison using the same compiler and settings and measured a 20% lead, with tuning still unfinished. The 2.2× throughput gap, he said, matched AMD’s internal projections all along. A separate endnote recalculates the per-core comparison on SPECrate 2017 using AMD’s own AOCC compiler and arrives at 1.7×, making 20% the more conservative of the two calculations.
AMD also showed a broader SPECrate 2017 ranking. Venice 9996 leads at 4900 (256 cores, 600W, $14,904 at 1Ku), followed by Turin 9965 at 3240, Intel’s Xeon 6980P at 2510 (128 cores, 500W, $13,955), Arm AGI at 1944 (136 cores, 300W), and Vera at 1459. The 9996, AGI, and Vera figures are AMD estimates; the Turin and Intel scores are published results. Against Intel, that works out to roughly twice the throughput at a comparable list price, or double the performance per dollar. On a per-core basis, a 128-core, 500W Venice configuration scores 1.3× the 6980P, while Arm AGI lands at 0.7×. Unlike the Vera comparison above, each vendor’s score here was produced with its own best toolchain: AOCC for AMD, OneAPI for Intel, and GCC 13 for Arm.
AMD also broke the comparison down by workload, with every result indexed to Intel’s 6980P at 1.0. On the cloud-native side, the 256-core Venice 9996 posts 3.5× on MongoDB, 2.9X on Redis, 3.7X on NGINX, and 2.6X on MySQL. Turin lands between 1.6X and 2.4X on the same tests, and Graviton5 between 1.2X and 1.5X.
In HPC, Venice scores 3.1X on GROMACS and NAMD, 2.9X on WRF, and 1.8X on Quantum Espresso. Memory configuration moves these numbers substantially. With standard 8,000 MT/s RDIMMs, Venice scores 2.81X the Xeon baseline on GROMACS; 12,800 MT/s MRDIMMs raise that to 3.13X, and the same upgrade takes WRF from 2.25X to 2.90X. AMD summarizes its HPC lead as anywhere from 1.8X to 3.5X depending on workload and memory. The Intel baseline ran 8,800 MT/s MRDIMMs, so the gap does not come from pairing upgraded AMD memory against a slow Intel configuration.
This brings us back to the 1.8X tokens-per-second claim. The hardware improvements behind it are easy to list: the 5GHz host part now carries 96 cores instead of 64, host memory bandwidth rises from 614GB/s to 1.6TB/s, and PCIe Gen 6 doubles the bandwidth of the CPU-to-GPU link.
The first thing to check is the baseline. AMD indexed this chart to Turin at 1.0 rather than to Intel, and placed the 6th Gen Xeon at 0.9, which is why the same claim approaches 2× when restated against the Xeon 6960P. The projected gain comes almost entirely from I/O bandwidth. AMD ran a CPU-offload test that streamed Qwen3-30B’s BF16 weights from host memory to the GPU and found the PCIe Gen 5 x16 receive path running at 89% to 95% of its theoretical ceiling, while host DRAM reads stayed below 10% of their theoretical ceiling. Decode speed was limited by the transfer, so doubling the link with PCIe Gen 6 yields a 1.8X to 1.9X improvement in this test. Venice is currently the only server CPU that offers PCIe Gen 6 to accelerators, so the advantage is real and, for now, exclusive. Its scope is narrow, though: the 1.8X describes one bandwidth-bound offload pattern, and it should not be read as a promise that GPUs serve every model 1.8X faster on Venice hosts. In hardware shipping today, a Turin host beats a Xeon 6960P by a geometric mean of 13% in time-to-first-token across vLLM and NIM workloads on the same 8X B200 system, with a best-case improvement of 36%.
The last claim is density: 49,152 Venice cores in a rack, against 36,864 for Turin and 22,528 for Vera, with each part carrying twice as many threads as cores. Of all the claims in the deck, this one changes the most once the endnotes are applied.
The headline is 2.2X Vera’s cores, but the Venice rack reaches it while drawing 269kW, compared to Vera’s 185kW, so the two racks are not compared at matched power. AMD’s endnotes supply normalized versions. With both racks held to a 100kW envelope, the 9996 delivers 2.08X Vera’s cores, 1.86X Turin, and 1.24X Intel’s 6980P. Substituting the 400W EPYC 9956 for the flagship, AMD estimates 1.91X Vera’s cores at 26% less power, resulting in 2.57X cores per rack watt. Depending on which power budget is held fixed, the lead lands between 1.9X and 2.2X, and, as with every Vera figure in this article, the NVIDIA rack is modeled from published specifications rather than measured hardware. The density advantage survives normalization; it is simply smaller than the 2.2X headline.
Set the individual claims aside: at the top end of the server CPU market, AMD currently has no direct rival. Intel’s best part trails Turin, the generation AMD is already replacing. The Arm challengers sit below Turin on every chart AMD showed. Vera has not shipped, and AMD’s estimate puts its throughput at less than half that of a Turin 9965, which has been on the market for a year and a half, with Venice roughly doubling Turin’s throughput again. That position has carried AMD to 46% of server CPU revenue, per Mercury Research. The market evidence points in the same way. Demand for top-end EPYC parts currently outruns supply, and lead times have stretched as a result.
We can add our own data point here. Our 314-trillion-digit Pi world record ran on a Dell PowerEdge R7725 with two 192-core EPYC 9965s and 1.5TB of DDR5, the same 384-core 2P configuration AMD models its Turin racks on. The computation kept every core loaded for 110 days and finished without a second of downtime; a single memory error or crash at any point would have scrapped the attempt. Power draw averaged about 1,600W, and the complete run consumed 4,305 kWh, or 13.7 kWh per trillion digits, against an estimated 33,600 kWh over roughly 225 days for the previous 300-trillion-digit record.
Venice is the strongest server CPU launch AMD has ever staged, and its real subject is breadth. One Zen 6 generation spans from a 256-core-density part through an enterprise socket and an 1152MB stacked-cache HPC chip to an LPDDR host node, so a customer can build every tier of a data center on the same architecture and software base. The numbers that anchor the launch hold up once the endnotes are read: roughly double Intel’s throughput at a comparable list price, a 20% per-core lead over Vera on a matched compiler, and rack density between 1.9X and 2.2X of NVIDIA’s host CPU, depending on the power envelope.
The commercial half of the story needs no forecasting. SP7 is in production now, with partner platforms due in Q4; SP8 follows in the first half of 2027, with Venice-X and Verano behind it. The company selling them already books 46% of server CPU revenue, and demand for its current parts far outstrips supply, so buyers wait in line rather than defect. Venice could slip a year, and the comparisons in this article would still read as leadership, because Turin already outscores everything else on the chart, shipped or unshipped. AMD is so far ahead that its nearest competitor, for the moment, is its own last generation.
The post AMD 6th Gen EPYC Venice: 256 Cores, 1.6TB/s, and the First PCIe Gen 6 Server CPU appeared first on StorageReview.com.
Finally, some good news after a long time. The ongoing NAND shortage is reportedly going to end next year. Noticeable Growth in NAND Supply to Put an End to Shortages by the End of 2027 as NAND Suppliers are Expected to Upgrade Production Lines While the DRAM market is expected to go through its worst-ever phase throughout the next two years, at the least the storage market is reportedly going to witness some relief. If you have been following the developments around the DRAM and NAND market, you might be aware that analysts predict instability for the next few years. […]
Read full article at https://wccftech.com/korean-us-and-japanese-suppliers-race-to-upgrade-fabs-ending-the-nand-flash-shortage-in-2027/
Following on from reveals at Computex last month, Phanteks is now bringing its new high-end Enthoo Server cases to the market, including both the Enthoo Pro 2 Server V2 and the Enthoo Elite Server
The Enthoo Pro 2 Server V2 features an all-metal exterior, but with lots of mesh for improved airflow. Inside, the chassis supports SSI‑EEB motherboards, 480mm and 360mm radiators, 11 PCIe slots and lots of storage, including up to 10 HDDs or 11 SSDs. Cooling support extends to 15 total fans, with targeted airflow over the CPU and GPU zones.
Phanteks is also launching the Enthoo Elite Server. As you would expect from a case like this, it supports both E‑ATX and SSI‑EEB motherboards, as well as dual PSU and multi‑GPU configurations, with 12 PCIe slots available. Cooling capacity is increased further, with support for up to 29 fans. The Elite Server also ships with additional wheels so it can easily be moved around.
Both cases are available starting this month, with the Enthoo Pro 2 Server V2 priced at £199.90, while the Enthoo Elite Server comes in at £349.90.
KitGuru Says: As we saw at Computex this year, a lot of PC case companies are now primarily focussed on the workstation / server market, a trend that we expect to continue.
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IBM has expanded its Power server lineup with new software to automate infrastructure management and application development. The announcements include IBM Power Autonomous Operations, an agentic control layer for system management, and the IBM Bob Premium Package for i, an AI-driven development assistant for IBM i environments. IBM also introduced the Power S1112, a compact single-socket Power11 server designed for on-premises AI inference.
The releases build on last year’s Power11 launch, which IBM positioned around availability, resiliency, and scale across on-premises and IBM Cloud deployments. The company frames these newer additions as extending autonomous IT capabilities across the platform, from application code through runtime operations.
IBM cited its Institute for Business Value 2026 Tech Leader Study, which projects enterprises will deploy an average of 1,661 AI agents by 2027, a 38% increase that IBM says leaves tech leaders managing hundreds of thousands of autonomous decisions daily, beyond the reach of manual governance. IBM’s stated rationale for these releases is that closing that gap requires infrastructure capable of self-management, freeing IT teams to focus on application work rather than routine operations.
Hillery Hunter, General Manager for IBM Power and CTO at IBM Infrastructure, said the goal is to let enterprises pursue rapid AI deployment without trading off system stability, positioning increased automation in Power as a way to handle routine availability, optimization, and security tasks while preserving control and resilience.
The Power S1112 is a single-socket Power11 system intended for organizations that are extending AI workloads to the edge or on-premises locations outside the data center. It uses Power11’s on-chip Matrix Math Acceleration (MMA) to handle inference locally with reduced latency.
IBM’s performance claims put the S1112 at twice the per-core performance of the Power S914 and three times that of the older Power S814, based on published CPW results for 4-core configurations. IBM also claims up to 69% better energy efficiency than the S914 in a smaller physical footprint; by IBM’s own footnote math, a 10-core S1112 delivers 539 CPW per watt against 319 for an 8-core S914.
| Power Servers | Chassis | Processor(s) | Number | Memory | Supported Operating Systems |
|---|---|---|---|---|---|
| IBM Power E1180 | 1 – 4 units of 5U system nodes and 2U system | Up to 4 | Up to 256 | 16 TB per node(up to 64 TB) | IBM AIX, IBM i, or Linux |
| IBM Power E1150 | 4U rack | Up to 4 | Up to 120 | 16TB | AIX |
| IBM Power S1124 | 4U rack | Up to 2 | Up to 60 | 8TB | AIX, IBM i, or Linux |
| IBM Power S1122 | 2U rack | Up to 2 | Up to 60 | 4TB | AIX, IBM i, or Linux |
| IBM Power S1112 | 2U rack | 1 | Up to 10 | 512GB DDR5 | AIX, IBM i |
Alongside the new server, IBM Technology Lifecycle Services is launching Power Expert Care Premium Essentials, an incident-focused support tier exclusive to the S1112. It includes priority access to IBM specialists, faster response times, and automated support tooling.
Power Autonomous Operations is IBM’s new control plane for automating day-to-day infrastructure tasks across Power environments. The platform continuously monitors system behavior to identify and address issues such as capacity constraints before they cause disruptions.
IBM reported internal testing results from an eleven-system Power environment, where the platform resolved a capacity-related issue in 3.33 minutes, compared to 52.59 minutes using traditional manual workflows, a roughly 15x reduction in resolution time. IBM says this is intended to eliminate hours of manual dashboard monitoring and analysis each month.
The platform includes an embedded AI agent that supports natural-language, chat-style interaction to manage and tune Power environments, which IBM says reduces the need for deep domain expertise for routine tasks.
IBM i remains widely used for core business operations across industries, but modernizing IBM i applications has historically required specialized RPG skills, limiting the pool of available developers. IBM Bob is positioned as an AI-driven development assistant that provides an agentic software development lifecycle experience for IBM i, aimed at helping engineers understand existing codebases, implement changes, and onboard onto IBM i development more quickly. Early adopters are already reporting results; Heartland Co-Op estimates new-to-platform developers understand complex IBM i applications 60% faster with Bob.
The Premium Package for i builds integrated support for IBM i standards into the development lifecycle, with the goal of expanding the number of engineers who can work on and modernize IBM i applications.
The Power S1112 is expected to be generally available on July 24. Power Autonomous Operations is scheduled for general availability on September 23, 2026. The IBM Bob Premium Package for i became generally available on June 24, 2026.
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Supermicro has introduced Kubernetes Edge AI Appliances, developed in partnership with Red Hat and Everpure. The pre-integrated systems combine Supermicro edge servers, Red Hat OpenShift, and the Portworx by Everpure Kubernetes data management platform to support AI inference, containers, and virtual machines across distributed sites.
The offering is positioned as a validated, software-preloaded deployment model for organizations that need to standardize AI infrastructure outside the data center. Supermicro is targeting edge environments where limited onsite IT resources, intermittent network connectivity, and the operational overhead of managing separate storage arrays can complicate deployment.
Red Hat OpenShift provides the Kubernetes and hybrid-cloud application layer, giving organizations a common environment for deploying, orchestrating, and managing workloads across edge, core, and cloud infrastructure. Supermicro’s role is to supply the compact edge compute platform and to distribute the combined hardware-and-software appliance.
Portworx by Everpure provides Kubernetes-native storage and data management. Rather than requiring a dedicated storage array at every site, the software aggregates local storage within Supermicro’s edge servers into a software-defined platform. Supermicro says the design supports autonomous operation during network interruptions, with high availability, data protection, and consistent storage policies maintained locally.
This matters in edge deployments such as retail locations, factories, and remote facilities, where applications may need to continue processing locally even if a connection to a central data center or cloud service is unavailable. The company is also positioning the platform for environments that require repeatable deployment and centralized operations across hundreds or thousands of sites.
The validation effort focuses on integrating the hardware, Kubernetes control plane, and persistent data layer into a supported stack. Supermicro says the appliance is designed to reduce deployment complexity while enabling the same operational framework to span edge systems and central infrastructure.
The announcement also aligns with Supermicro’s broader Data Center Building Block Solutions strategy, which combines validated compute, storage, networking, software, and services components. That model allows customers to deploy configurations ranging from individual edge servers to rack-scale infrastructure while maintaining a common platform approach.
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ASRock Rack has developed an unlikely edge server based on NVIDIA's industrial SoC, Thor. The Blackwell-era chip is being used to power the 2UXGI-THOR, a server aimed at the industrial and medical markets
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IBM is expanding its mainframe lineups with new single-frame and rackmount z17 and LinuxONE 5 offerings for smaller customers. As well, the company is releasing an 18U LinuxONE box for new customers called the LinuxONE Express
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IBM has expanded its IBM z17 and IBM LinuxONE 5 portfolios with new rack-mount and single-frame configurations, marking the first time rack-mount systems are available across the company’s entire IBM Z and LinuxONE lineup. The additions are designed to provide enterprises with greater deployment flexibility while maintaining the performance, security, and software ecosystem of IBM’s flagship platforms.
The announcement targets organizations facing record-low data center vacancy and rental rates exceeding $400 per kW/month, figures IBM cites from CBRE’s 2026 Global Data Center Trend Report. With enterprise workloads continuing to grow, particularly those incorporating AI, IBM is positioning the new systems as a way to improve infrastructure density and deployment flexibility without requiring organizations to compromise on resiliency or performance.
IBM said the expanded portfolio enables customers to deploy IBM Z and LinuxONE systems in configurations that better align with existing data center layouts and operational requirements.
The new IBM z17 and IBM LinuxONE 5 models support up to 82 processor cores and 18TB of memory across two processor drawers, representing approximately a 20% increase in core count and a 12% increase in memory capacity over previous comparable systems.
IBM also announced new IBM Crypto Discovery & Inventory capabilities that give security teams a consolidated view of cryptographic assets across the enterprise. The tools are intended to help organizations assess readiness for post-quantum standards and simplify ongoing cryptographic management.
The portfolio now includes several deployment options:
IBM said the rack-mount designs allow customers to integrate IBM and non-IBM infrastructure within the same rack, improving space utilization and simplifying deployment into existing data centers.
Like the previously announced z17 and LinuxONE 5 systems, the new models support multi-model AI inference using the IBM Telum II processor, Red Hat OpenShift AI, and the IBM Spyre Accelerator. IBM said the platform enables both predictive AI and generative AI processing within transactional workloads.
Security capabilities include confidential computing, enterprise secrets management, and post-quantum cryptography, which are now standard features across z17 and LinuxONE Rockhopper 5 systems.
IBM also announced new Crypto Discovery and Inventory capabilities that provide organizations with centralized visibility into cryptographic assets across the enterprise. The tools are intended to help security teams assess readiness for post-quantum cryptography and simplify ongoing cryptographic management.
Alongside the hardware announcements, IBM introduced new software designed to simplify system administration and application modernization.
IBM Infrastructure Management for IBM Z and IBM LinuxONE consolidates provisioning, configuration, and operational management into a single interface. The platform supports Terraform and other Infrastructure-as-Code frameworks, allowing organizations to automate deployment and orchestration while providing a visual representation of system I/O topology and configuration.
IBM also announced IBM COBOL Elevate for z/OS, which is designed to improve the modernization and performance of COBOL applications running on IBM z17. The software aims to help organizations optimize existing applications without requiring rewrites or extensive specialized expertise.
IBM said the new management capabilities are intended to reduce operational complexity while helping organizations maximize the value of existing IBM Z and LinuxONE environments.
The new IBM z17 Single Frame, IBM z17 Rack Mount, IBM LinuxONE Rockhopper 5, and IBM LinuxONE 5 Express systems are scheduled to become generally available on August 12, 2026.
IBM Infrastructure Management for IBM Z and IBM LinuxONE will be generally available on August 14, 2026.
IBM COBOL Elevate for z/OS is scheduled for general availability on September 18, 2026.
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At Computex 2026 we came across one of the first servers based around Arm's new AGI server CPU. ASRock Rack had their 1U4E1S-ARM, a 1U single-socket server that will be the backbone of future data center systems
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The developers of the PlayStation 4 emulator ShadPS4 have announced ShadNet. This open-source custom server system enables online multiplayer without requiring a connection to the official PlayStation Network (PSN) or a PlayStation Plus account.
ShadNet emulates network services, allowing PC players to access multiplayer features in emulated titles like Bloodborne. However, the development team has been transparent about current limitations, noting that the ecosystem is still in the early testing phase. This infrastructure uses a similar approach to RPCN, the custom server solution widely used for the PlayStation 3 emulator RPCS3. Currently, only score tracking works within the new framework, though account registration has already opened on the emulator's official website.
The announcement follows the project's largest update to date, shadPS4 v0.16.0, which arrived in late May. That release introduced major updates, including a new config system, local multiplayer support, improved Vulkan API stability, expanded support for Neo GPU features, and increased compatibility with PS4 Pro-enhanced titles.
Sony hasn't taken action against the emulator over its two-year development span. Despite this lack of intervention, introducing a custom server platform that completely bypasses PSN requirements could attract legal scrutiny in the future.
KitGuru says: Have you ever tried shadPS4?
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AMD has introduced the Versal Premium Gen 2 Memory-on-Package (MoP) adaptive SoCs, adding integrated LPDDR5X memory directly into the device package to increase bandwidth while reducing board complexity and footprint. The new devices target applications that require high memory throughput within constrained power and space budgets, including networking, physical AI, aerospace and defense, test and measurement, and professional video systems.
Unlike traditional designs that rely on external DRAM, the Versal Premium Gen 2 MoP architecture integrates up to 32GB of LPDDR5X memory into the package, providing up to 288GB/s of memory bandwidth. According to AMD, the approach reduces board area by up to 60% compared to equivalent external memory implementations while eliminating much of the complexity associated with high-speed memory routing. AMD bases the bandwidth and footprint figures on its Versal Premium Gen 2 MoP 2VP3622 device measured against a monolithic Versal Premium Gen 2 adaptive SoC paired with external memory.
The integrated memory architecture is designed to improve bandwidth, reduce latency, and lower power consumption compared to conventional board-level memory implementations. By removing the need for external LPDDR5X layout, designers can simplify PCB design, reduce validation requirements, and shorten development cycles.
AMD positions the platform for compact embedded and edge systems with limited board space. The smaller footprint enables designs targeting standards such as EDSFF and 3U VPX, while supporting telecom and defense platforms that often face strict thermal and mechanical constraints.
The devices also integrate PCIe 6.0 and CXL 3.1 hard IP operating at up to 64GT/s, enabling high-speed communication with processors such as AMD EPYC CPUs. Combined with LPDDR5X operating at up to 9,000Mb/s, the architecture is intended to support data-intensive workloads while enabling system architects to expand memory resources through CXL memory pooling and expansion technologies.
For long-lifecycle deployments, AMD states that the Versal Premium Gen 2 MoP family supports industrial operating temperatures ranging from -40°C to 110°C and is backed by more than 15 years of product availability. The company notes that using LPDDR5X instead of HBM helps avoid the shorter refresh cycles common in data center memory products, reducing the likelihood of hardware redesigns due to component availability.
Security capabilities are also integrated into the platform. PCIe Integrity and Data Encryption (IDE), introduced with PCIe 6.0, protects data moving across PCIe links, while integrated DDR memory encryption secures data stored in memory without consuming programmable logic resources. The devices also include hard 400G High-Speed Crypto Engines for secure, high-bandwidth processing.
AMD summarized the primary design goals as eliminating traditional trade-offs among memory bandwidth, physical footprint, power consumption, and product longevity. By integrating memory directly into the adaptive SoC package, the company says customers can build higher-performance systems while reducing board-level engineering effort and accelerating deployment.
Development can begin immediately with the standard Versal Premium Series Gen 2 devices currently shipping, supported by existing Vivado and Vitis development environments, compatible IP, and reference designs. AMD expects Versal Premium Gen 2 Memory-on-Package devices to begin sampling at the end of 2026, with production shipments planned for the second half of 2027.
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JetCool has introduced a liquid-cooled version of the Dell PowerEdge XE7745, combining the server, direct-to-chip liquid cooling, rack infrastructure, deployment services, lifecycle support, and unified warranty coverage into a single integrated offering. The solution is delivered factory-tested and ready for deployment, simplifying the rollout of high-density AI and HPC infrastructure while reducing operational complexity.
The Dell PowerEdge XE7745 is designed for AI, HPC, and GPU-accelerated workloads. It supports dual 5th Gen AMD EPYC processors and up to eight NVIDIA RTX PRO 6000 Blackwell GPUs, providing a dense compute platform for enterprise AI environments.
JetCool integrates its SmartPlate direct-to-chip liquid-cooling technology to meet the thermal demands of modern accelerator-based servers. The cooling system removes heat directly from CPUs and GPUs and is designed to support sustained thermal loads of up to 8 kW per server, reducing the likelihood of thermal throttling. Compared to the air-cooled configuration, JetCool reports the design lowers CPU temperatures by up to 7% and GPU temperatures by up to 11%, widening thermal margin under load. The efficiency gains follow from the same approach: lowering fan speeds by up to 70% and fan power consumption by up to 50% can reduce total server power consumption by up to 30%, and acoustic output drops by up to 23 dB.
The company also cites efficiency improvements from the liquid-cooled design. By lowering fan speeds by up to 70% and fan power consumption by up to 50%, total server power consumption can be reduced by up to 30%. Acoustic output is also significantly reduced, with JetCool reporting up to a 23 dB reduction in server noise.
By removing heat more efficiently at the component level, the system frees additional power and cooling capacity at the rack level. This allows organizations to increase compute density within existing data center footprints without requiring major facility upgrades.
The platform is designed to simplify deployment into existing environments. JetCool says its low-flow cooling architecture enables organizations to replace lower-density servers while continuing to use existing facility water loops. The company supplies the complete rack-level cooling infrastructure, including racks, mounting hardware, coolant distribution units (CDUs), manifolds, and fluid distribution equipment as a factory-integrated system.
Beyond the hardware, JetCool packages server integration, commissioning, deployment, ongoing maintenance, and warranty support into a single offering. This provides enterprises with a single point of accountability for both the server platform and the liquid cooling environment, reducing the coordination typically required among multiple vendors.
The solution is manufactured and supported through Flex, providing customers with access to global manufacturing, supply chain, and service resources to support deployments across multiple regions.
JetCool founder Bernie Malouin, who also serves as Vice President at Flex, said increasing AI infrastructure density requires organizations to deploy significantly more compute capacity while minimizing operational risk. He said that delivering the Dell PowerEdge XE7745 as a fully integrated, liquid-cooled platform with deployment and lifecycle services is intended to simplify adoption and help customers maximize hardware performance within existing facilities.
The liquid-cooled Dell PowerEdge XE7745 is available directly from JetCool. Additional information is available at https://jetcool.com/Dell.
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Supermicro has announced an expanded lineup of edge computing systems built around Intel Core Ultra Series 3 and Intel Core Series 2 processors, as well as Intel Arc Pro B-series GPUs. The portfolio spans fanless industrial units, short-depth 1U rack-mount servers, and mini-tower configurations, targeting AI inference and intelligent automation deployments in retail, manufacturing, physical security, transportation, and logistics.
Supermicro VP of IoT/Embedded and Edge Computing, Mory Lin, said the company’s latest Intel-powered edge systems are designed to address the growing demand for real-time inference, low latency, and energy efficiency at the point of data generation. Intel Edge Computing Group CVP and GM Dan Rodriguez added that combining Intel Core Ultra processors and Arc Pro GPUs with Supermicro’s edge-optimized platforms enables faster and more efficient deployment of AI workloads across diverse real-world environments.
The SYS-E103-14P is a compact, DIN-rail-mountable fanless system built on Intel Core Ultra Series 3 processors. The platform integrates a GPU and an NPU, delivering up to 180 TOPS of combined AI performance and enabling computer vision and industrial automation workloads without requiring a discrete accelerator. The system supports up to 128GB of DDR5 memory, broad I/O connectivity, and an operating temperature range of 0°C to 45°C, making it suited for rugged edge environments where power efficiency and physical durability are priorities.
The SYS-521AD-LN2 is a compact mini tower powered by Intel Core Series 2 processors with up to 12 high-performance P-cores and up to 64GB of DDR5 memory. The system is designed for localized AI inference, model development, and fine-tuning, and supports compact GPU accelerators, including the Intel Arc Pro B50 and NVIDIA RTX PRO 2000 Blackwell. The dual-GPU option gives customers flexibility to match accelerator performance to specific workload requirements.
Supermicro has also refreshed the SYS-111AD-WN2R short-depth 1U server and the SYS-E300-13AD5 compact edge system to support Intel Core Series 2 processors. Both platforms retain their existing form factors, allowing organizations to upgrade compute and AI performance without changing their physical deployment footprint. Both systems also gain DDR5 memory support, improving memory bandwidth and responsiveness for next-generation workloads.
Supermicro is now supporting the full Intel Arc Pro B-series GPU lineup across its edge AI server portfolio, adding discrete graphics acceleration for AI inference and visual computing workloads.
The Arc Pro B70 delivers up to 367 TOPS with up to 32GB of VRAM, targeting high-throughput AI pipelines that require large memory capacity. The Arc Pro B60 provides up to 197 TOPS with expanded memory bandwidth and multi-GPU scalability for larger AI workloads. The Arc Pro B50 is a low-power option that delivers up to 170 TOPS and is well-suited for space-constrained edge deployments and workstations with limited thermal and power budgets.
Alongside the new systems, Supermicro highlighted its Data Center Building Block Solutions (DCBBS) portfolio, which provides validated, modular AI infrastructure components ranging from individual servers and networking equipment to full rack-scale and data center-level configurations. The approach is intended to give customers flexibility in how they scale AI deployments while maintaining validated interoperability across hardware, software, and services.
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Dell Technologies has introduced the PowerEdge XE8812, a new liquid-cooled server platform designed for large-scale inference and high-performance computing workloads. The system joins the Dell AI Factory with the NVIDIA portfolio. It is built around the NVIDIA Vera Rubin NVL4 architecture, offering up to 144 GPUs per rack in a dense rack-scale configuration.
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The announcement reflects growing demand for infrastructure capable of supporting increasingly complex AI and simulation workloads. Organizations across scientific research, engineering, sovereign AI initiatives, and genomics are requiring greater compute density, memory capacity, and power efficiency than previous-generation systems can provide.
The Dell PowerEdge XE8812 is a fanless, direct liquid-cooled platform targeting environments running large-scale simulations and data-intensive workloads. Dell positions the system for applications such as molecular modeling, multiphysics simulation, and foundation model development.
Based on NVIDIA Vera Rubin NVL4, the platform increases host memory capacity, CPU core counts, GPU memory, and overall compute resources compared to systems built on NVIDIA GB200 NVL4. Dell notes that CPU core counts increase from 144 to 176, and that the platform carries 50% more memory per socket and GPU memory than the prior generation, enough to keep larger AI models and simulations resident in memory.
Keeping datasets and models resident in memory reduces reliance on staging and swapping operations, both of which introduce microsecond to millisecond latency and sharply cut effective bandwidth. That penalty matters most in HPC and AI environments, where data movement increasingly governs overall application performance.
The platform also leverages NVIDIA CUDA-X libraries to accelerate scientific computing and AI workloads, enabling organizations to run larger simulations and models without distributing workloads across additional infrastructure.
Dell plans to deliver the XE8812 in an Open Rack v3 (ORv3)-based rack architecture supporting up to 144 GPUs per rack and power delivery exceeding 300kW. The system employs direct liquid cooling for both CPUs and GPUs, enabling higher component density and improved thermal efficiency.
The ORv3-based design provides a modular architecture intended to simplify deployment and integration into large-scale data center environments. Dell also emphasizes operational management capabilities through its infrastructure management portfolio.
Integrated Dell Remote Access Controller (iDRAC) provides remote deployment, monitoring, and update capabilities for PowerEdge systems. At the rack level, Dell Integrated Rack Controller and OpenManage Enterprise provide telemetry, monitoring, and automated leak detection designed to improve operational visibility and reduce infrastructure risk.
The company is pairing the new platform with Dell PowerRack, a factory-integrated rack-scale deployment model designed to reduce implementation complexity for large AI and HPC clusters.
Dell says PowerRack systems are delivered as pre-validated configurations, allowing organizations to move more quickly from installation to production workloads. Combined with Dell ProDeploy white-glove services, the approach replaces manual rack integration with production-ready racks that Dell says can be up and running with live workloads in just over six hours.
Dell reported continued growth for its Dell AI Factory initiative, with more than 5,000 customers deploying AI infrastructure globally.
Several high-profile deployments highlight the range of supported workloads.
In the United States, Dell, NVIDIA, and the National Energy Research Scientific Computing Center (NERSC) are building the Doudna supercomputer at Lawrence Berkeley National Laboratory. The system will use Dell PowerEdge XE8812 servers equipped with NVIDIA Vera Rubin NVL4 technology and NVIDIA Quantum-X800 InfiniBand networking to support large-scale scientific computing and data-intensive research.
In France, AI company InstaDeep is scaling its Kyber supercomputing cluster using Dell AI Factory infrastructure. The system delivers approximately 0.5 exaFLOPs of FP16 performance and supports industrial design applications, including automated printed circuit board design.
In the UK, the Wellcome Sanger Institute uses Dell PowerEdge XE-Series servers with NVIDIA GPUs to support genomic research. The institute now produces a fully assembled genome every 7 hours and manages more than 100 PB of curated genomic data on-premises, work that has contributed more than 70% of the genomes in the global Earth BioGenome Project.
In Australia, Monash University has deployed the MAVERIC supercomputer in partnership with Dell, NVIDIA, and CDC Data Centres. The system uses liquid-cooled Dell PowerRack infrastructure and PowerEdge XE9712 servers based on NVIDIA GB200 NVL72 technology to support AI and data-intensive research spanning cancer detection, climate action, and genomics.
Dell said the PowerEdge XE8812 will be available globally in early 2027.
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In the world of PC gaming performance analysis, we tend to obsess over frame times, and for good reason. A simple average FPS number can be extremely misleading, while a frame time graph can immediately show you whether a game is delivering frames smoothly or whether it is suffering from stutters, hitches, CPU/platform bottlenecks, or other forms of inconsistent frame pacing. However, as useful as frame times are, there is one major problem with relying on them alone: they do not always tell us what the player actually sees on the monitor. This is especially important nowadays, as modern PC […]
Read full article at https://wccftech.com/display-times-frame-times-and-the-truth-about-smoothness/
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