d-Matrix Joins the NVIDIA NVLink Fusion Platform

By: Cliff Robinson

12 September 2026 at 21:42

d-Matrix and NVIDIA announced that d-Matrix will use NVLink Fusion to scale up and out with its next-gen Raptor AI accelerators

The post d-Matrix Joins the NVIDIA NVLink Fusion Platform appeared first on ServeTheHome.

Wccftech
AMD Says A Hybrid-Bonded 3D DRAM Is 17x More Energy Efficient Than An HBM Stack That Relies On Microbumps, But Thermal Hurdles Block Commercialization
1 September 2026 at 15:40

AMD Says A Hybrid-Bonded 3D DRAM Is 17x More Energy Efficient Than An HBM Stack That Relies On Microbumps, But Thermal Hurdles Block Commercialization

Wccftech

By: Rohail Saleem

1 September 2026 at 15:40

The silicon industry has arrived at a consensus that the HBM pathway to unlock incremental AI compute is stalling, especially as converting silicon wafers into an HBM stack yields far less usable capacity than commodity DRAM, prompting the wider industry to start experimenting with SRAM-only decode, Processor-In-Memory (PIM) within LPDDR, CXL pooling, and 3D DRAM. Of course, it is the 3D DRAM architecture that is considered somewhat of a panacea at the moment, as highlighted by AMD's recent admission as to its phenomenal energy efficiency. Even so, odious hurdles continue to prevent the commercialization of this promising technology. AMD has […]

Read full article at https://wccftech.com/amd-says-a-hybrid-bonded-3d-dram-is-17x-more-energy-efficient-than-an-hbm-stack-that-relies-on-microbumps-but-thermal-hurdles-block-commercialization/

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d-Matrix’s Raptor 3D DRAM Achieves SRAM-Class Bandwidth at 1/10th the HBM Power by Dropping PHY & Fusing DRAM Beneath the Compute
23 August 2026 at 22:05

d-Matrix’s Raptor 3D DRAM Achieves SRAM-Class Bandwidth at 1/10th the HBM Power by Dropping PHY & Fusing DRAM Beneath the Compute

Wccftech

By: Hassan Mujtaba

23 August 2026 at 22:05

d-Matrix proposes 3D DRAM as a solution to the rising AI data problem using stacked memory to deliver SRAM-Like bandwidth with magnitudes higher efficiency than HBM. The Time For 3D DRAM Is Now, Says d-Matrix, As It Unveils its "Raptor" 3D DRAM Solution With SRAM-Class Bandwidth As AI model sizes and KV cache continue to expand, capacity and bandwidth constraints become more visible. So far, all major DRAM manufacturers are working toward next-gen solutions that stack logic with DRAM, but d-Matrix says "The Time For 3D DRAM" is now. Today, there are two leading memory technologies for AI workloads: SRAM […]

Read full article at https://wccftech.com/d-matrix-raptor-3d-dram-achieves-sram-class-bandwidth-at-1-10th-the-hbm-power/