AMD has introduced the Ryzen AI Max 400 series of processors for local AI development platforms. Serving as an architecture refresh to the previous Ryzen AI Max (PRO) 300 series Strix Halo hardware, the new silicon combines Zen 5 CPU cores, RDNA 3.5 integrated graphics, a dedicated NPU, and AMD PRO enterprise management features. Consumer-targeted iterations of these processors are scheduled to debut later this year.

The primary update centres on the integrated memory controllers, which have been modified to support up to 192GB of LPDDR5X unified memory via a 4-channel, 256-bit interface. Users can manually partition this pool to allocate up to 160GB directly to the integrated graphics subsystem, providing the capacity needed to run LLMs with more than 300 billion parameters. Performance modifications include a maximum GPU boost frequency increase to 3.00GHz, a maximum CPU boost clock increase to 5.20GHz, and a 10% performance uplift for the built-in NPU to reach 55 TOPS.

The product stack consists of three distinct processor designs. The top-tier Ryzen AI Max+ PRO 495 features 16 cores and 32 threads, boosting up to 5.20GHz, a fully enabled 40-compute-unit iGPU (Radeon 8065S), 80MB of cache, and a 55 TOPS NPU. The mid-range Ryzen AI Max PRO 490 scales back to a 12-core, 24-thread configuration, clocking up to 5.00GHz, paired with a 32-compute-unit iGPU (Radeon 8050S), 76MB of cache, and a 50 TOPS NPU. The entry-level Ryzen AI Max PRO 485 maintains the 32-compute-unit iGPU (Radeon 8050S) and 50 TOPS NPU, but uses an 8-core, 16-thread CPU layout, boosting up to 5.00GHz and accompanied by 40MB of cache.

KitGuru says: These aren't for the general consumer yet, but consumer versions of these chips are expected at a later date. 

AMD's roadmap for integrated graphics is becoming increasingly complex as the company appears to be looking to bridge the gap between its current offerings and the next-generation UDNA architecture. New commits to the LLVM compiler suggest that the previously spotted GFX1170 target, branded as RDNA 4m, is expanding, as two additional software IDs, GFX1171 and GFX1172, have surfaced.

As spotted by Phoronix in the LLVM compiler, these GFX117x targets are not “true” RDNA 4 parts, which reside in the GFX12 branch. Instead, they appear to be a custom evolution of RDNA 3.5. By backporting specific RDNA 4 modules into the GFX11 instruction set, AMD is creating what we might call RDNA 3.5+. This hybridisation adds support for INT8 and FP8 data types, which are essential for running the machine-learning-based upscaling and frame-generation features of FSR 4.

The decision to modify RDNA 3.5 rather than jump straight to a full RDNA 4 iGPU isn't clear, but one might guess it's due to limitations shrinking the full RDNA 4 architecture down for things like thin and light laptops, where a smaller power envelope is crucial. By updating RDNA 3.5 with WMMA (Wave Matrix Multiply-Accumulate) and SWMMAC instructions, AMD might be ensuring that its upcoming APUs can leverage FSR Redstone features.

While “Medusa Point” is expected to use an RDNA 4m iGPU, “Medusa Halo” is expected to leap straight to the RDNA 5/UDNA microarchitecture.

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KitGuru says: While RDNA 4m is mostly a rebrand of RDNA 3.5, the addition of native FP8 support could be enough to enable FSR 4.