Volta has emerged from stealth with a vertically integrated AI infrastructure platform designed to combine capital formation, powered land, data center development, GPU compute, software, and operations under one organization.

The company is targeting a financing gap in the AI infrastructure market. While the largest technology companies can fund large GPU deployments directly from their balance sheets, AI labs, AI-native companies, and enterprises often rely on constrained public-cloud capacity. Volta’s premise is that compute should be financed as an infrastructure asset, using long-term contracted cash flows and institutional capital rather than relying solely on corporate balance sheets or venture financing.

Founded by CEO Ricard Boada and Chief Corporate Development Officer Sofia Gumuzio, Volta describes its model as “The Utility of Compute.” The company aims to develop dedicated AI factory capacity with infrastructure-style financing, standardized operations, and more predictable pricing structures. “Compute has become a new infrastructure asset class, with AI models and applications as the verticals built on top,” said co-founder and CEO Ricard Boada. Its approach combines site development, power procurement, data center infrastructure, accelerated compute, cloud software, and cluster operations.

Volta’s launch is anchored by a $10 billion strategic partnership with an unnamed AI lab to develop an AI factory in Norway alongside Bitdeer. The planned facility is expected to provide 133MW of capacity and use NVIDIA Vera Rubin systems. It represents the first site in Volta’s stated development pipeline, which exceeds 1GW of near-term power capacity across North America and Europe.

Using NVIDIA DSX for Site Development

The company said it plans to develop sites using NVIDIA’s DSX platform and is targeting multiple gigawatts of deployed capacity by 2030. Specific deployment schedules, GPU quantities, network architecture, and contract terms for the Norway project were not disclosed.

To fund future developments, Volta has established an AI Infrastructure Program with Azora. The program is intended to provide $5 billion in financing for future AI factories developed by Volta. Azora manages more than $20 billion in real estate and infrastructure assets, according to Volta.

The financing structure gives Volta access to non-dilutive infrastructure capital for project development. For customers and strategic partners, the company expects the model to provide greater financing certainty and reduce the effective cost of capital associated with deploying dedicated AI capacity. For institutional investors, the structure is designed to offer direct exposure to AI infrastructure assets supported by long-term contracted revenue.

Volta also disclosed that it has completed seed and Series A funding rounds at a $2.4 billion valuation. The rounds were led by Azora, Andreessen Horowitz, Altimeter, and NVIDIA, with participation from strategic investors including Michael Dell’s family office and Matter Venture Partners.

Volta has also selected Dell Technologies for its first AI factory, with Dell saying the Norway deployment will use Dell AI solutions, including PowerEdge XE9812 servers and Dell services, to support deployment at scale.

Earlier this year, Volta acquired Genesis Cloud technology, adding public AI cloud and bare-metal cluster-management capabilities. The acquisition gives Volta a software layer for delivering GPU infrastructure as a service while supporting dedicated cluster operations. The company said the software stack will allow it to combine AI cloud capabilities with new AI factory developments and its infrastructure financing model.

Volta currently employs approximately 100 people across London, Palo Alto, and New York. Its organization spans capital formation, infrastructure development, engineering, and software operations, reflecting the company’s plan to operate across both the financial and technical layers of AI infrastructure deployment.

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IBM has announced a multi-year, $240 million agreement with Together AI to deploy a dedicated NVIDIA HGX B300-based AI inference cluster on IBM Cloud. Together AI plans to use the environment to deliver inference services for open-source models, expanding its AI Native Cloud platform for enterprise customers.

The deployment is positioned as IBM Cloud’s first dedicated large-scale inference cluster built around NVIDIA HGX B300 systems, following the Grace Blackwell capacity IBM added through CoreWeave last year. It will also use NVIDIA Spectrum-X Ethernet networking, creating an AI factory architecture intended to support high-throughput, low-latency inference workloads. IBM says the deployment is built to deliver 30x more AI factory output compared to prior generations. However, workload-level performance will depend on model architecture, precision, batch size, and serving configuration.

Together AI offers infrastructure and software services spanning inference, model training, fine-tuning, and agentic AI workflows. The company reports that its inference platform now serves 400 trillion tokens monthly. The new IBM Cloud deployment is intended to add GPU capacity for production inference while improving performance and token economics for organizations deploying open-weight and open-source models at scale.

“Together AI is proud to lead the way in bringing production inference to market with NVIDIA’s latest AI infrastructure on IBM Cloud,” said Vipul Ved Prakash, CEO at Together AI. “Working alongside IBM with NVIDIA accelerates our mission to make advanced AI broadly accessible through open source and to empower builders with the infrastructure and platform capabilities they need to build the future.”

The collaboration brings together IBM Cloud’s enterprise infrastructure, NVIDIA’s HGX B300 compute systems and Spectrum-X Ethernet fabric, and Together AI’s inference platform. The resulting stack is designed to support organizations that need to deploy and operate AI services across cloud and hybrid environments, particularly for workloads where throughput, response time, and infrastructure utilization directly affect operating costs.

“Enterprises are in a race to adopt agentic AI at scale to drive real business outcomes,” said Alan Peacock, general manager of IBM Cloud. “IBM and NVIDIA are delivering scalable, economical, enterprise-grade AI infrastructure that can help Together AI accelerate innovation for the next generation of AI infrastructure.”

Together AI selected IBM and NVIDIA based on their GPU infrastructure roadmaps and their ability to provide capacity at the pace needed for AI service expansion. The company raised an $800 million Series C at an $8.3 billion valuation in July to expand its AI Native Cloud platform.

IBM characterized the agreement as part of its broader work with NVIDIA across AI infrastructure and software. The companies have also referenced joint work around GPU-native data analytics, unstructured data extraction, hybrid infrastructure, and consulting services. For IBM Cloud customers, the Together AI deployment adds another route to production-grade inference infrastructure built on NVIDIA’s latest HGX platform and high-performance Ethernet networking.

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Lumilens has emerged from stealth with a portfolio of optical interconnect products targeting two networking constraints in large AI clusters: scale-out connectivity between racks and scale-up connectivity among GPUs within a compute domain.

The company said it has begun shipping its first scale-out product to production AI data centers for a hyperscale customer under a multi-billion-dollar agreement. Lumilens also announced over $700 million in Series C funding, co-led by Atreides Management, Bain Capital Ventures, Meritech, Seligman Ventures, and Spark Capital. The round values the company at $5.51 billion and brings total funding to more than $900 million.

Lumilens was founded in early 2024 and is positioning its technology around the growing role of networking in AI infrastructure design. As GPU cluster sizes grow, network bandwidth, optical component availability, power consumption, and cabling density are becoming primary constraints alongside accelerator supply.

At the scale-out layer, large GPU deployments require many optical transceivers and fiber connections. Lumilens cited an estimated need for more than 2.4 million transceivers and more than five million fiber strands for a 400,000-GPU data center. The company also pointed to McKinsey projections that 800G optical transceiver production could fall 40 to 60 percent short of demand through 2027, with 1.6T shortfalls of 30 to 40 percent through 2029.

Within the rack, Lumilens is addressing scale-up networks, where tightly coupled GPUs have historically used short-reach copper electrical links. Signal integrity limits the practical reach of those connections to roughly 1.5 meters at AI data rates, generally constraining scale-up fabrics to a single rack. Extending these domains across larger GPU counts requires optical I/O closer to the compute silicon.

The Lumilens product portfolio includes near-packaged optics (NPO) and co-packaged optics (CPO) for scale-up systems, plus 800G and 1.6T pluggable optical transceivers for scale-out fabrics. The scale-up products move optical interfaces near or alongside GPU packages, replacing longer electrical paths and enabling larger, more tightly coupled compute domains.

The company’s scale-out modules target rack-to-rack and cluster-level links, where high-bandwidth optics replace copper connections at greater distances while reducing power and cabling constraints. Lumilens said its roadmap extends beyond 1.6T optics but did not disclose specific product availability dates or interface specifications.

Lumilens builds its products on a platform it calls LumiCore, which combines silicon photonics, mixed-signal ICs, electrical-optical interposers, and optical systems. The company said it develops these elements internally to improve design control and shorten customer qualification cycles.

Manufacturing is central to the company’s strategy. Lumilens said it developed an electrical-optical interposer to simplify photonic-chip assembly, supported by proprietary process recipes, robotics, and automated test systems. Production is expected to scale through manufacturing partners and Lumilens-operated facilities.

Founder and CEO Ankur Singla said hyperscale operators need both increased optical capacity for existing AI fabrics and a path toward clusters that directly connect thousands of GPUs. “The constraint on AI has shifted from how many GPUs you can buy to how many you can connect,” Singla said. Lumilens is targeting both requirements with a unified approach spanning pluggable optics, silicon photonics, and optical system integration.

The new funding will support expansion across silicon development, systems, software, process engineering, and high-volume manufacturing operations. Lumilens said its team includes personnel with experience from Cisco, Juniper Networks, Meta, Marvell, Lumentum, and Coherent. Singla previously founded Contrail Systems, acquired by Juniper Networks, and Volterra, acquired by F5. Co-founder and CTO Ted Schmidt was previously a Distinguished Engineer at Juniper.

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Smart IOPS and H3 Platform have announced an AI compute storage platform targeting up to one billion random-read IOPS. The proposed system combines Smart IOPS’ Unobtanium T50 solid-state devices with an air-cooled H3 Platform appliance designed around NVIDIA accelerated computing and networking technologies.

The platform targets data-intensive AI inference and analytics workloads that require GPUs to access large datasets through highly parallel, fine-grained I/O. It is designed to support NVIDIA’s Storage-Next initiative and SCADA, or Scaled Accelerated Data Access, programming model. These technologies enable GPU-initiated access to NVMe storage when application working sets exceed local GPU memory.

By reducing the distance between GPU compute and storage, the architecture is intended to reduce CPU control-path overhead and help keep accelerators supplied with data. The approach is aimed at workloads such as graph neural networks, vector search, recommendation systems, retrieval-augmented generation, embedding stores, and other sparse analytics applications that generate large volumes of small, random requests.

“AI infrastructure is entering a phase in which storage must behave less like a passive repository and more like an active extension of the compute fabric,” said Ashutosh Das, CEO of Smart IOPS.

Smart IOPS Unobtanium T50

The Unobtanium T50 is a PCIe Gen6 x4, NVMe 2.0 device in an E3.S form factor. Smart IOPS specifies up to 50 million random-read IOPS and 10 million random-write IOPS at a 512-byte block size. Sequential performance is rated at up to 28 GB/s for reads and 24 GB/s for writes. Sequential throughput in that range matches PCIe Gen6 enterprise SSDs already entering mass production; the 512-byte random-read figure is the specification that stands apart.

Four T50 devices can provide a stated aggregate target of up to 200 million random-read IOPS at the device level. Smart IOPS positions that capability as a match for the I/O requirements of next-generation PCIe Gen6 x16 GPUs, including NVIDIA Rubin. Actual performance will depend on workload characteristics, software, PCIe topology, system configuration, and other system-level factors.

The T50 uses the Smart IOPS TruRandom controller architecture with widely available TLC NAND operated in pseudo-SLC mode. The company says this approach allows the devices to use multiple qualified NAND suppliers while retaining access to the manufacturing scale and supply-chain capacity of the broader flash industry. The controller can also support specialized low-latency NAND where the workload or deployment economics justify it.

H3 Platform Appliance

H3 Platform is developing an air-cooled appliance with four NVIDIA RTX PRO 6000 Blackwell Server Edition GPUs, four NVIDIA ConnectX-8 network adapters, and 20 E3.S 2T storage slots. Each slot is designed to support up to 60 watts, providing the power and thermal capacity required by high-performance storage devices.

With 20 slots populated by T50 devices, the system is designed to reach a target of up to one billion random-read IOPS. The configuration is intended to balance GPU compute, networking, and storage connectivity in a single platform for evaluating and deploying GPU-initiated, small-block storage workloads.

“The next wave of AI systems must be designed as an integrated data path,” said Brian Pan, founder and CEO of H3 Platform, “not as disconnected compute, network and storage components.” The design places high-IOPS E3.S storage alongside GPUs and high-speed network adapters while retaining an air-cooled form factor.

High IOPS is relevant to these workloads because bandwidth alone does not describe how effectively a storage system handles irregular, concurrent accesses. Small-block requests generated by many GPU threads can expose queuing and synchronization overhead in CPU-orchestrated storage architectures. A higher-IOPS, lower-latency device can service more concurrent requests and potentially reduce the time GPUs spend waiting for data.

Smart IOPS and H3 Platform expect evaluation samples and systems to become available in the first quarter of 2027. Production availability is planned for the second quarter of 2027. The specifications, configurations, and schedules remain preliminary and may change. Customer qualification, software ecosystem readiness, and any NVIDIA validation or approval are separate processes and are not implied by the announcement.

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Netlist and Samsung have signed a five-year set of agreements covering patent cross-licensing, DRAM and NAND supply, technology cooperation, and the settlement of all pending litigation between the companies. “We’re excited to renew this partnership and look forward to working closely with Samsung,” said Netlist CEO C.K. Hong, a nod to the joint development agreement the two companies signed in 2015 before years of litigation. “These strategic agreements reflect the companies’ shared commitment to innovation in the AI-memory space and validates the value of Netlist’s IP.”

The deal gives Samsung a worldwide license to specified Netlist patents, including technology related to server DIMMs and High Bandwidth Memory. The license is royalty-bearing for Samsung, while Netlist receives a royalty-free license to specified Samsung patents. Samsung will pay Netlist an upfront patent license fee of $239 million, or approximately $200 million after Korean withholding taxes, followed by quarterly license payments of up to $32.9 million gross through the second quarter of 2031. The recurring payments are based on a revenue formula and remain subject to contractual adjustments and refund rights.

Netlist said the arrangement could generate up to $750 million in net license fees over its five-year term. The agreement replaces years of patent disputes across U.S. district court, International Trade Commission, and Patent Trial and Appeal Board proceedings. Those disputes included a $303 million jury award in favor of Netlist against Samsung in 2023, although prior litigation outcomes had remained subject to appeal and patent-validity proceedings.

A separate supply agreement allows Netlist to purchase up to $300 million annually in DRAM and NAND products from Samsung Semiconductor, with aggregate purchasing capacity of up to $1.5 billion over five years. The agreement gives Netlist a defined source of memory components that can be used in its own specialized products or supplied to customers through its existing sales channels. The supply limit represents a maximum purchasing capacity, not a minimum purchase commitment.

Samsung Semiconductor also agreed to buy 10 million shares of Netlist common stock for $1 million in a private transaction. The shares will be subject to a five-year transfer restriction, with 20% released on each of the first four anniversaries and the balance released in the fifth year.

The companies also signed a five-year ITC cooperation agreement under which Samsung will provide specified information, documents, or declarations for Netlist’s future ITC actions involving third parties. Netlist’s dispute resolution with Samsung therefore does not end its broader IP enforcement activity.

While technical development deliverables were not disclosed, the natural candidates are the areas Netlist has been developing publicly: hybrid CXL memory and low-power MRDIMM designs. Those technologies address two emerging infrastructure concerns: expanding memory capacity at a lower cost than DRAM-only configurations, and reducing power consumption in next-generation high-density memory modules.

Primary terms are disclosed in Netlist’s Form 8-K filing.

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SK hynix used Future of Memory and Storage 2026, held August 4 to 6 at the Santa Clara Convention Center, to showcase a comprehensive “full-stack” AI memory portfolio spanning HBM, server DRAM, NAND, and CXL expansion. The company’s presence centered on the transition toward agentic AI and the need to shift from individual product performance to integrated memory architectures. It shared the show with Samsung’s 3D memory roadmap, which we covered separately.

Tiered Memory and High Bandwidth Flash

SK hynix delivered the show’s third keynote under the theme “Orchestrating Efficient AI Infrastructure through Tiered Memory in the Era of Agentic AI,” presented by Kim Chun-sung, executive vice president and head of Solution Development, and Kang Uk-song, vice president and head of Next Generation Product Planning. Their argument: as AI agents process exponentially larger datasets, memory architecture must evolve into a “Tiered Memory” system. “What determines overall efficiency is where each memory tier, HBM, DRAM, NAND (HBF), and SSD, is positioned and how it is connected to minimize data movement,” Kim said.

A significant part of this tiered strategy is High Bandwidth Flash (HBF). SK hynix describes HBF as a new memory category that applies TSV stacking, similar to HBM, to balance the capacity of traditional NAND with the bandwidth of DRAM. Positioned as a tier between ultra-high-speed HBM and high-capacity SSDs, HBF is intended to boost system scalability while lowering operational costs.

Exhibition Highlights: HBM4 and 375-Layer NAND

The exhibition floor featured several key hardware milestones:

• Next-Gen HBM: SK hynix placed an HBM4 model side by side with a model of NVIDIA’s next-generation Vera Rubin accelerator to show how the two companies’ technologies come together. Displays included physical units of the 12-layer 48GB HBM4E it began sampling in July, 16-layer 48GB HBM4, and 12-layer 36GB HBM3E.
• 375-Layer 4D NAND: This represents the company’s first NAND product utilizing wafer bonding. It delivers 2.5 times the performance per watt of the previous generation. Enterprise SSDs based on this NAND are slated for mass production in the first half of 2027.
• High-Capacity eSSDs: The PS1101, a QLC-based eSSD, offers about 55% higher performance than the previous 176-layer generation. Sample shipments for major cloud service providers are scheduled to begin in August 2026.
• Edge AI Solutions: LPDDR6, LPDDR5/5X, UFS 4.1, and UFS 5.0 products were showcased as answers for Physical AI and low-power edge devices, with SK hynix saying it will apply data-aware placement and media-aware tiering in its mobile and client SSD products for edge inference.

CXL and Compute-in-Memory Demonstrations

SK hynix demonstrated the practical application of Compute Express Link (CXL) through multiple live scenarios. One demo featured CXL Pooled Memory to manage KV cache in distributed AI agent systems, significantly improving performance over traditional network-based communication. Another demonstration used CMM-Hybrid to prefetch KV cache into DRAM while maintaining the primary cache on SSD for high-capacity storage.

The company also introduced CMM-Ax, a compute-in-memory solution that embeds computing capabilities within memory to accelerate long-context LLM inference. SK hynix’s supporting research on efficient long-context LLM serving was accepted by MICRO 2026, which the company notes is the most prestigious conference in computer architecture.

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AMD has entered into a definitive agreement to acquire Toronto-based Taalas, a developer of specialized AI inference silicon. The acquisition is intended to expand AMD’s inference capabilities as AI deployments shift toward real-time and high-volume production workloads, where efficiency, memory movement, and optimized dataflows are increasingly important. It lands two days after AMD put its own inference stack in front of enterprises with Instinct Coder.

Founded in 2023 and led by co-founder and CEO Ljubisa Bajic, Taalas develops inference hardware tailored to specific AI models. Its approach is designed to reduce compute and memory bottlenecks common in general-purpose architectures by optimizing the inference dataflow around the target model. This can improve efficiency for workloads where conventional GPU and accelerator architectures may carry overhead associated with broader programmability.

AMD expects to incorporate Taalas technology into its accelerator roadmap and develop system-level inference solutions using AMD Instinct GPUs. Vamsi Boppana, senior vice president of the Artificial Intelligence Group at AMD, framed the deal around breadth rather than replacement, saying the company is “building a full-stack AI platform that gives customers the flexibility to deploy the right compute solutions for every AI workload” and that Taalas strengthens that portfolio “by delivering differentiated inference performance and efficiency.” The technology will sit alongside AMD’s broader AI portfolio, including Helios rack-scale systems, Instinct accelerators, EPYC CPUs, ROCm software, and its partner ecosystem.

The transaction also brings Taalas’ engineering organization into AMD’s AI group. Bajic described the company’s premise as building “the hardware around the model,” and said joining AMD provides “the scale, engineering resources, and global reach to accelerate our innovation.” AMD positioned the acquisition as a way to add differentiated silicon and engineering expertise for inference, complementing its existing compute platform and expanding options for deploying specialized AI workloads.

The acquisition remains subject to customary closing conditions and regulatory approvals. Financial terms were not disclosed. AMD also stated that it intends to retain and grow Canadian AI and semiconductor talent following the transaction.

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Synopsys has announced what it describes as the industry’s first complete Compute Express Link (CXL) 4.0 intellectual property suite. The portfolio combines a CXL controller, IDE security modules, a PCIe 7.0-based physical layer, and verification IP for system-on-chip designers building AI infrastructure. The verification piece has been shipping since December 2025, when Synopsys called it the first commercially available CXL 4.0 verification IP; the controller, security modules, and PHY are what complete the set.

The announcement shows a broader shift in AI system design. As model sizes and context windows expand, memory capacity, bandwidth, and access latency increasingly limit performance. Large language model inference depends on moving model weights, key-value caches, and shared state between processors, accelerators, and memory. Goldman Sachs Research estimates global AI token consumption could increase 24 times by 2030, reaching about 120 quadrillion tokens per month.

CXL is designed to address these requirements through a cache-coherent interconnect operating over the PCI Express physical layer. The standard enables CPUs, XPUs, accelerators, and memory devices to share resources while supporting memory expansion, pooling, and fabric-based architectures.

CXL 4.0 Doubles Bandwidth

CXL 4.0 increases link speed to 128 GT/s, equaling the bandwidth of PCIe 7.0. Synopsys states that the new specification maintains the latency characteristics of CXL 3.x while doubling available system bandwidth.

The specification also adds bundled port capabilities. Four x16 links provide more than 2 TB/s of aggregate bandwidth, while eight x16 links exceed 4 TB/s. CXL 4.0 supports up to four retimers and native x2 link widths, extending connectivity options for rack-scale systems. The other significant addition in the 2025 specification is on the reliability side, with memory RAS enhancements covering granular event reporting, Post Package Repair, and flexible memory sparing.

These capabilities support disaggregated compute and memory architectures. Synopsys claims CXL-based key-value cache offload delivers three to six times the performance of SSD-based alternatives at 128 GT/s. The company also cites CXL.mem load-to-use latency below 200 nanoseconds and rack-scale memory pools exceeding 100 TB. According to Synopsys, these capabilities could reduce inference costs by 50% to 100%, depending on system configuration and workload.

Design Challenges Extend Beyond the Controller

Implementing CXL 4.0 requires more than adding a new controller to an SoC. AI system designers must support multiple CXL generations and manage differences in memory capacity, bandwidth, availability, and system topology. CXL 4.0 maintains backward compatibility with earlier versions, allowing new designs to use existing infrastructure while migrating to higher-speed fabrics.

Security is another consideration. Cloud and multi-tenant AI deployments require authenticated and encrypted coherent memory access anchored to a hardware root of trust. Synopsys says its IDE implementation provides that protection without adding cycle-level latency in CXL.cache and CXL.mem skid modes.

The AI infrastructure market also pressures development schedules. System designers must typically accommodate rapidly changing accelerator architectures and hyperscale deployment requirements. Delays in verification, interoperability testing, or physical-layer qualification can therefore affect the entire SoC schedule.

Synopsys CXL 4.0 IP Portfolio

The Synopsys CXL controller supports CXL 4.0 at 128 GT/s, along with CXL 3.x, 2.0, and 1.x. It includes bundled ports, port-based routing, and a 256-byte FLIT mode to reduce latency. The company says a single license covers the supported CXL generations and includes PCIe 7.0 fallback without requiring a separate PCIe 7.0 IP license.

The IDE security modules use AES-GCM encryption and authentication and support TSP and TDISP features for confidential computing. Synopsys also states that the implementation is designed for FIPS 140-3 certification readiness.

The CXL physical layer is based on a silicon-proven PCIe 7.0 SerDes operating at 128 GT/s. Synopsys says the PHY is hardened for process nodes from 5nm to 2nm and includes low-jitter tolerance and low-latency forward error correction.

The verification IP is the oldest piece of the stack. Synopsys introduced it in December 2025 as the industry’s first commercially available CXL 4.0 VIP, supporting the full 128 GT/s data rate along with IO throttling and streamlined port negotiation, and offering migration paths from CXL 3.0 and PCIe 7.0. The verification environment is intended to support compliance and interoperability testing before tape-out, reducing the risk that standards validation becomes a late-stage development bottleneck.

Synopsys positions the unified architecture to support CXL migration across multiple product generations. The company cites more than 25 years of PCIe development, over 3,800 PCIe design wins, and more than 170 CXL controllers and PHYs shipped. It has taken a similar portfolio approach to other AI fabrics, including the Ultra Ethernet and UALink IP it introduced for accelerator clusters.

Part of a Broader HPC IP Portfolio

The CXL 4.0 offering is part of Synopsys’ broader high-performance computing IP portfolio. The portfolio includes interface IP for CXL, PCIe, UCIe, UALink, Ultra Ethernet, ESUN, and high-speed Ethernet PHYs supporting 224G and 448G links.

It also includes foundation IP such as memory, logic libraries, and standard cells for advanced process nodes. Security components cover hardware roots of trust, physically unclonable functions, post-quantum cryptography, security accelerators, and interface protections, including PCIe and CXL IDE, IME, MACsec, and UALinkSec.

Synopsys also offers pre-integrated IP subsystems intended to reduce the amount of integration and verification required for XPU, accelerator, and hyperscaler SoC designs. Together, these components target the interconnect, memory, security, and compute requirements of rack-scale AI infrastructure.

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AMD, Spectro Cloud, and Supermicro have announced AMD Instinct Coder, a validated enterprise inference platform intended for AI coding workloads. The solution combines AMD Instinct GPU accelerators, Supermicro AI infrastructure, and Spectro Cloud’s PaletteAI Inference Launchpad to provide a packaged option for deploying private and hybrid AI inference environments.

The architecture is designed for enterprises, cloud providers, and sovereign AI operators that need to balance local processing, access to frontier models, operational governance, and token consumption. Rather than directing all coding-agent requests to external large language models, AMD Instinct Coder uses policy-based routing to determine whether a request is served by a locally deployed model or forwarded to an external frontier-model endpoint.

This approach targets workloads where routine coding, code generation, summarization, and similar tasks can be handled locally, while more complex reasoning or specialized capabilities remain available through external models. The platform is intended to reduce dependence on a single model provider while keeping sensitive code, prompts, and contextual data within controlled infrastructure where appropriate. The partners claim the arrangement can reduce AI coding token costs by up to 70%, with AMD’s own materials framing the same figure as total cost of ownership and citing payback in as little as six months. Neither figure has been independently verified.

The announcement arrives as organizations scale AI coding tools across development teams and automated workflows. Gartner stated in its June 24, 2026 report, Gartner Predicts AI Coding Costs Will Surpass Average Developer’s Salary by 2028 as Token Consumption Surges, that token costs could outpace productivity gains without a structured operating model. AMD Instinct Coder addresses that concern through model routing, metering, quotas, and workload policies.

The initial configuration is expected to use AMD Instinct MI325X GPUs. Each MI325X accelerator includes 256GB of HBM3E memory and up to 6TB/s of peak memory bandwidth, targeting memory-intensive generative AI inference workloads. AMD positions the platform around its Instinct accelerator portfolio and ROCm software ecosystem, aiming to support locally operated inference without requiring organizations to assemble and validate the complete hardware and software stack independently. Local inference runs a GLM-5.2 model optimized through AMD Inference Microservices, and the platform exposes token quotas, audit trails, and cost visibility through Grafana and Prometheus dashboards.

Specifications

Supermicro provides the underlying enterprise AI infrastructure. Its supported systems include air- and liquid-cooled eight-GPU platforms compatible with AMD Instinct MI325X and MI350 Series accelerators. Supermicro’s contribution includes pre-validation, rack integration, and system qualification, intended to reduce deployment complexity and shorten the transition from delivered infrastructure to production inference.

Spectro Cloud PaletteAI Inference Launchpad provides the operational software layer. The platform supports routing across local and frontier models, workload-specific policy enforcement, token metering, consumption quotas, and multi-tenant separation for teams and users. The software is designed to maintain local execution for suitable workloads while retaining fallback connectivity to externally hosted frontier models.

The resulting architecture uses tiered inference, assigning model endpoints based on required performance, sensitivity, model capabilities, cost objectives, and available infrastructure capacity. For platform teams, this creates a way to standardize how AI coding demand is provisioned and governed across internal users and applications. Dan McNamara, senior vice president and general manager of Compute and Enterprise AI at AMD, framed the shift as AI coding moving from an individual developer tool to an enterprise platform decision. BMC is among the early users, with Tom Davies, vice president of SaaS operations, describing AMD Instinct Coder as a cost-effective, high-performance inference layer for the company’s Helix Agentic Engineering work.

The initial AMD Instinct Coder configuration is expected to be delivered on Supermicro systems using AMD Instinct MI325X GPUs, with the partners demonstrating the platform at Ai4 in Las Vegas this week. Final product configurations, availability, regional support, and pricing remain subject to partner validation and approval, so the specifications above describe the reference build rather than a shipping SKU with published pricing. Organizations interested in evaluation can contact Spectro Cloud through its Get Started page.

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Object First reported a 148% year-over-year increase in bookings during the second quarter of 2026, reflecting continued demand for the company’s Ootbi immutable backup appliances as organizations strengthen defenses against ransomware and other cyberattacks.

Bookings in EMEA increased 205% compared with the same period last year, while the Americas grew 111%. Six-figure deals rose 133%, including two transactions valued at more than $1 million. The company also reported a 74% year-over-year increase in transacting customers, which now span 45 countries. Transacting partners increased by 65% during the quarter.

Demand was particularly strong in public-sector environments. In one example, a Portuguese higher education institution selected Object First’s on-premises immutable backup storage to protect against cyber threats while simplifying backup operations. The company also credited Veeam’s go-to-market reach for two seven-figure deals involving public-sector and manufacturing organizations. Veeam has owned Object First since acquiring the company in January 2026, though the two continue to run separate partner programs.

Object First launched Fleet Manager during the quarter. The secure, cloud-based service is designed to centralize administration of distributed backup appliances deployed in Veeam environments. Its multi-tenant architecture targets enterprises and service providers that need to manage multiple customer or organizational deployments from a single platform.

The company positions immutable backup storage as a core layer in ransomware recovery strategies, an approach we examined in our hands-on look at how Ootbi scales from edge to enterprise. By preventing protected backup data from being modified or deleted during a defined retention period, the technology is intended to provide a recoverable copy if production systems are compromised. Object First also said its platform supports operational resilience and requirements related to regulatory compliance and data sovereignty.

Object First CEO David Bennett said customer attitudes toward immutable storage have shifted from treating it as a recommended best practice to treating it as a required security control. He added that demand has continued despite hardware supply chain constraints, with early preparation allowing the company to maintain appliance shipments. Bennett credited the company’s work alongside Veeam and its focus on purpose-built backup storage for the quarter’s growth. Object First also picked up two honors at the 2026 UK Storage Awards during the period, taking Ransomware Company of the Year and Enterprise Backup Hardware Vendor of the Year.

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Broadcom has issued updates for VMware vDefend and VMware Avi Load Balancer, enhancing security, performance, deployment, and automation features for VMware Cloud Foundation 9.1 environments. These updates include vDefend SSP 5.2, vDefend 9.1.1, Avi Load Balancer 32.1.4, and the vDefend and Avi Conversion Tool 3.0.

The updates focus on private cloud deployments where IT teams implement distributed security controls across virtual machines, Kubernetes services, AI infrastructure, and application APIs. Broadcom frames these releases within a multi-layer model integrating east-west microsegmentation, intrusion prevention, malware analysis, web application firewall features, API security, and application delivery.

Faster vDefend Deployment and Expanded On-Premises Security

The vDefend Security Services Platform adds a 1-2-3 deployment workflow for Advanced Threat Prevention. This process reduces the operational work needed to deploy threat prevention services by providing a guided path for policy assessment, rule recommendations, and deployment.

The workflow integrates with vDefend Distributed Firewall, using workload-level visibility to assess security posture and recommend segmentation policies. The goal is to shorten deployment timelines for advanced threat prevention and reduce manual policy creation by security teams.

Broadcom also added on-premises malware prevention through local sandboxing. Static and dynamic malware artifacts can be analyzed within the customer environment without sending data to a cloud service. This option suits organizations with data sovereignty, regulated data, or isolated environment requirements.

All vDefend capabilities now support air-gapped environments. Broadcom said threat intelligence can be updated offline, allowing disconnected environments to receive current threat data while maintaining network isolation.

Native API Protection for VMs, Kubernetes, and AI Workloads

Avi Load Balancer now adds native API protection for VMs, vSphere Kubernetes Services, and AI workloads. This combines web application firewall controls with API protection, creating a WAAP capability to identify exposed APIs, apply protections, and improve application-layer visibility.

APIs have become a common attack surface in private cloud deployments, especially as applications decompose into microservices exposed through Kubernetes-based services. Integrating API protection with Avi Load Balancer can reduce the number of separate security products needed to protect application traffic while keeping policy enforcement close to the load balancing and application delivery layer.

Higher Distributed Firewall and IDPS Performance

Broadcom also reported higher throughput figures for vDefend Distributed Firewall and Distributed Intrusion Detection and Prevention System deployments.

For Distributed Firewall, Broadcom cites throughput up to 22Gbps on servers with 25GbE NICs, a 129 percent increase, and up to 75Gbps on systems with 100GbE NICs, a 241 percent increase. At scale, Broadcom reports Distributed Firewall throughput up to 75Tbps per VMware Cloud Foundation instance.

The company also increased distributed IDPS performance up to 17Gbps per server, an 89 percent increase. Broadcom reports scale-out IDPS throughput up to 17Tbps per VCF instance. All performance figures are based on internal Broadcom test results from July 2026.

These capabilities support virtual patching at the workload layer. Distributed IDPS can inspect traffic and block exploit attempts within the hypervisor layer, providing compensating control while organizations test and deploy software patches. This is especially relevant for AI infrastructure and other data-heavy environments where lateral traffic volumes can be substantial.

Reduced SSP Footprint and Avi Throughput Gains

vDefend SSP 5.2 introduces a two-node deployment model. Broadcom said this configuration can reduce the physical infrastructure needed to operate SSP by up to 33 percent while retaining lateral segmentation functionality.

Avi Load Balancer also receives scale-out performance improvements. Broadcom reports up to 12.25Tbps throughput per controller instance, an 88 percent increase. For large application environments, this targets higher application delivery density without proportional expansion of load balancing infrastructure.

AI Assistant and Firewall Migration Automation

Both vDefend Distributed Firewall and Avi Load Balancer now include an AI Assistant to simplify administration, troubleshooting, and remediation workflows. Broadcom did not provide implementation details but positioned it as an embedded tool to reduce operational complexity in security and load balancing operations.

The updated vDefend and Avi Conversion Tool, vACT 3.0, adds migration capabilities for moving from legacy agent-based firewalls to vDefend Distributed Firewall. The tool automates elements of firewall policy migration and reduces the effort of transitioning to a distributed, hypervisor-based segmentation model.

The new features are compatible with VMware Cloud Foundation 9.1.

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Etched raised $300 million in a Series C funding round at a $10.3 billion valuation, announced in late July, less than a month after the company emerged from stealth. Sequoia led the round, which included participation from a16z, Jane Street, Diffusion, and SK Hynix. The company described it as the highest valuation achieved in a Sequoia-led Series C.

Etched plans to use the funding to expand production and accelerate customer deployments. In addition to its previously constructed Taiwan factory, the company has opened an 80,000-square-foot facility approximately 15 minutes from its main office. The 10 MW Milpitas site will support a new product introduction lab, an in-house surface-mount technology line, prototyping, and broader deployment operations.

The company is focused on purpose-built systems for AI inference, which it views as a central and expanding component of AI workloads. Etched is targeting higher inference throughput, lower operating costs, and improved energy efficiency to support larger-scale deployments than current data center infrastructure can economically provide.

Multiple Model Support

Etched says its hardware supports multiple model architectures and is not limited to a single model type. Its inference clusters currently run large mixture-of-experts models, including DeepSeek and Qwen, as well as Mamba, a state-space model with a different architecture from transformer-based systems. The approach is intended to allow customers to use the same infrastructure as model architectures evolve.

The company is developing two technologies for its rack-scale systems. Low Voltage Inference, or LVI, is designed to increase FLOP density within an existing power envelope. Conventional systems often encounter thermal limits that constrain clock speeds before reaching their maximum theoretical compute performance. Etched uses hardware and system co-design to target higher throughput at lower power and cost.

Combining SRAM and HBM

Cluster Scale Memory, or CSM, combines SRAM and HBM in a memory system designed for an entire cluster rather than an individual processor. The architecture creates a shared SRAM pool across the scale-up domain and connects it using a proprietary high-bandwidth, low-latency interconnect. Etched says this design is intended to improve memory access latency while avoiding the cost, yield, reliability, thermal, and compute tradeoffs associated with SRAM-only systems and 3D DRAM-based approaches.

Etched said demand for its inference systems is exceeding supply as customers move from evaluation to production deployments. The company has rapidly expanded its team to 400 people, with engineers recruited from NVIDIA, Broadcom, Google TPU, SK Hynix, and high-frequency trading firms.

The company operates from a San Jose office that includes an NPI prototyping facility and a 2 MW data center running Etched hardware continuously. Sequoia partner Sonya Huang said Etched had made unusual progress for a semiconductor company in less than three years. She said purpose-built inference compute could become dominant as inference expands.

Etched co-founder and CEO Gavin Uberti said the company believes frontier AI infrastructure requires more than incremental hardware improvements. He characterized the company’s approach as a first-principles redesign of the technology stack focused on improving inference speed, cost efficiency, and scalability.

Co-founder and President Rob Wachen said the company has significant work ahead to reach gigawatt scale and is partnering with AI infrastructure investors to move faster. He added that the team is working around the clock with early customers to bring its first product to life.

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The U.S. Department of Energy has selected IBM for a Phase I Genesis Mission project focused on AI-assisted quantum application development. The company also plans to provide up to $50 million in access to IBM quantum systems for DOE national laboratories and their partners over the next five years.

The Genesis Mission is building a national scientific-computing framework that brings together AI, classical high-performance computing, quantum computing, scientific instruments, and research data. IBM’s selection adds a quantum component to the first set of projects under the Genesis Mission Request for Applications process.

This work complements the DOE’s planned computing infrastructure at Oak Ridge National Laboratory. As previously reported, AMD’s Lux system is expected to become the first fully operational Genesis Mission platform, with funded projects slated to begin using it in October 2026. Lux combines AMD Instinct MI355X GPUs, EPYC CPUs, and Pensando networking to support AI services, conventional HPC workloads, simulation, and data-intensive research workflows. IBM’s contribution is directed at extending that model to include quantum resources for workloads where classical systems and AI alone are insufficient.

AI-Assisted Quantum Application Development

IBM’s Phase I project will examine a reversed workflow for identifying quantum computing applications. Rather than beginning with a scientific problem and searching for a quantum algorithm, IBM plans to start with known quantum algorithms and use an agentic AI research assistant to locate scientific problems in published literature that meet the algorithms’ requirements.

The system would review research papers, identify possible algorithm-to-problem matches, assess them against human-defined criteria, and produce an explanation for researchers to evaluate. The objective is to reduce the manual effort involved in surveying scientific literature and uncover application candidates that may otherwise be missed.

The DOE’s Phase I awards are intended to establish and test research workflows before larger-scale funding and deployment. Teams will evaluate whether AI-enabled approaches can accelerate discovery, improve predictive accuracy, improve experimental workflows, or identify new research opportunities.

Quantum Systems Available to DOE Labs

IBM said it will make systems including the 156-qubit IBM Quantum Heron and 120-qubit IBM Quantum Nighthawk available to DOE national labs and their research partners. The company will also provide technical support for integrating quantum hardware with the labs’ existing AI and HPC environments.

IBM operates 15 quantum systems and reports more than 97 percent uptime across the fleet. Its latest Nighthawk architecture includes 120 programmable qubits, supports more than 5,000 quantum operations, and delivers throughput of up to 100,000 circuits per second.

The program’s practical value will depend on workflow integration rather than quantum hardware alone. Quantum systems are likely to be used selectively, with AI narrowing large research spaces and conventional GPU-accelerated supercomputers handling simulation and data processing. Quantum processors can then be directed toward specific portions of a workload that are difficult to model efficiently with classical methods.

Molten Salt Research Illustrates the Model

IBM pointed to a recent collaboration with Oak Ridge National Laboratory and Cleveland Clinic as an example of this approach. The organizations used a quantum-centric workflow to study molten salts relevant to tritium fuel production for fusion-energy systems.

AI agents searched and filtered candidate materials from ORNL’s molten-salt research archive, which spans roughly 70 years of research. GPU-accelerated supercomputers modeled the shortlisted materials, while quantum computers were applied to the most computationally complex aspects of the simulations.

That division of labor aligns with the broader Genesis Mission approach. Lux is expected to provide a near-term platform for integrated AI and HPC workflows, including simulations, digital twins, autonomous laboratory environments, and persistent AI services. IBM’s project introduces quantum computing as an additional resource that can be connected to those workflows as suitable scientific applications emerge.

The Genesis Mission roadmap also includes Discovery, an exascale-class system planned for delivery at ORNL in 2028. Discovery is expected to use 6th Gen AMD EPYC “Venice” CPUs, AMD Instinct MI430X GPUs, and an HPE Cray platform with DAOS storage. Together, Lux, Discovery, and associated quantum resources outline a DOE strategy centered on progressively integrating AI, HPC, data, and emerging compute architectures into scientific research workflows.

IBM already works with DOE laboratories including Lawrence Berkeley, Oak Ridge, and Los Alamos. The Genesis Mission project formalizes another avenue for evaluating where quantum computing can deliver measurable value alongside the AI and HPC infrastructure being deployed at national laboratories.

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Marvell used FMS 2026 to introduce new memory infrastructure technologies aimed at helping hyperscalers and cloud providers scale memory independently from compute. The portfolio spans server-level AI storage, rack-scale CXL memory expansion and pooling, and pod-level optical shared memory.

The releases target growing memory demands from agentic AI inference. Larger models, longer context windows, and expanding key-value caches are increasing requirements for memory capacity, bandwidth, and connectivity. In traditional server-attached architectures, these demands can lead to processor stalls and inefficient data movement.

Memory disaggregation allows memory to be expanded, pooled, and shared independently of compute resources. Marvell said its approach is designed to improve memory accessibility, reduce latency and data movement, and increase processor utilization. The goal is to produce more tokens within existing data center power and space constraints.

Will Chu, executive vice president and general manager of Custom Cloud Solutions at Marvell, said AI infrastructure is moving from isolated servers toward integrated systems that combine compute, memory, and connectivity. He added that more independent memory scaling is necessary to improve resource utilization and manage the cost and power requirements of AI deployments.

Server-Level AI Storage

The Marvell Bravera SC6 PCIe 6.0 SSD controller is designed to support AI inference workloads that require frequent movement of KV-cache data between high-bandwidth memory and SSD storage. Marvell said the controller provides twice the speed of its Bravera SC5 PCIe 5.0 predecessor.

By improving cache transfer performance, the SC6 is intended to increase storage efficiency for AI, cloud, and enterprise workloads. The controller also targets lower write amplification and longer NAND service life. Support for NAND from multiple suppliers gives hyperscalers greater flexibility when sourcing and deploying SSDs.

The Bravera SC6 is expected to begin sampling in the fourth quarter of 2026.

Rack-Scale Memory Expansion and Pooling

Marvell’s Structera X memory expansion solutions build on the company’s existing Structera CXL platform and are designed to help hyperscalers address memory-intensive AI workloads through larger and more flexible memory pools. Developed with hyperscaler partners, the platform supports memory expansion and resource sharing across servers.

Structera X is intended to improve the utilization of existing memory investments while accommodating larger models, longer context windows, and increasing KV-cache requirements. By separating memory capacity from individual server configurations, the platform can support more adaptable CXL-based expansion and pooling architectures.

Marvell said the approach is designed to improve infrastructure utilization and operational efficiency while reducing total ownership costs. It also establishes a foundation for future CXL memory pooling and sharing systems.

Pod-Level Optical Shared Memory

Marvell’s Photonic Fabric components include optical memory modules, network interface controllers, and chiplets for a shared-memory architecture spanning multiple racks. The system is designed to connect XPUs and racks across distances of up to 50 meters.

The architecture supports up to 32TB of warm KV-cache offload with high bandwidth and low latency. Instead of retrieving KV-cache data from storage, AI systems can access it from the shared optical memory tier. Marvell said this can improve inference throughput, support larger models and longer context windows, and increase token efficiency.

The company projects up to two to three times higher token throughput within existing data center space and power constraints. Actual performance will depend on system configuration, workload characteristics, and the implementation of the surrounding AI infrastructure.

Marvell is showing the portfolio at FMS 2026, booth #805. The announcement lands in a week dominated by inference-memory news, and it dovetails with NVIDIA’s Storage-Next and SCADA push: Marvell has pointed to that architecture requiring PCIe Gen7 SSDs sustaining 100 million IOPS, and controllers like the Bravera SC6 are the stepping stones toward drives built for GPU-driven small-block access.

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VDURA and Wasabi Technologies have formed a technology alliance to connect GPU-adjacent AI data infrastructure with predictably priced, S3-compatible cloud storage.

The partnership targets AI factories, neoclouds, and enterprise high-performance computing environments that need to keep active datasets and model checkpoints close to GPUs while moving inactive data to lower-cost cloud capacity. The approach is intended to support long-term retention, data protection, governance, and reuse without consuming performance storage capacity.

The core operating model is to keep data near compute resources while it is active and move it when it becomes idle. AI infrastructure teams frequently retain inactive datasets, checkpoints, and model artifacts on high-performance systems because data migration can introduce operational complexity, access constraints, and uncertain cloud costs. This can leave expensive performance capacity occupied by data that no longer requires low-latency access. It can also make retained data more difficult to secure, govern, and reuse.

VDURA provides the performance tier for active AI workloads. Its platform supports dataset staging, model loading, training, checkpointing, and inference through GPU-adjacent parallel file system performance, RDMA data paths, and POSIX compatibility. The platform combines NVMe flash and HDD storage with a native S3 interface under a unified global namespace.

Wasabi supplies the cloud storage tier for active archiving and long-term preservation. Data no longer used directly by GPUs, including datasets, checkpoints, model versions, and derived artifacts, can be stored in Wasabi for protection, compliance, disaster recovery, and sharing across sites or computing environments. The data remains available for future retraining, model comparison, and governance activities.

Under Wasabi’s standard plan, the service does not charge per-GB egress or API request fees. The company positions this pricing model as a way for organizations to forecast the cost of retaining and reusing AI data without variable retrieval charges.

Tiered data placement is already common in large-scale cloud infrastructure, where high-performance systems are paired with cost-efficient capacity platforms. VDURA and Wasabi are applying the same model to AI infrastructure through two specialized systems connected by open interfaces rather than a single closed platform.

VDURA CEO Ken Claffey said the performance infrastructure used for GPU processing is optimized for speed and active workloads. At the same time, checkpoints, dataset versions, and model artifacts require secure and predictable long-term storage. He described the partnership as a way to integrate data movement into the AI lifecycle while combining VDURA’s high-performance storage with Wasabi’s cloud object storage.

Laurie Mitchell, senior vice president of global marketing at Wasabi Technologies, said AI data remains valuable after a training run. It can support future models, provide an audit trail for governance, and serve as a baseline for comparison. She said the alliance is designed to simplify connections between GPU-adjacent infrastructure and independent, S3-compatible cloud storage, letting organizations keep control of their data and costs without locking either into a hyperscaler.

The alliance will be on display at Ai4 2026, running August 4 to 6 at The Venetian in Las Vegas, where Wasabi is exhibiting at booth #935.

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Samsung used the Future of Memory and Storage (FMS) 2026 conference to present its latest memory and storage technologies for artificial intelligence and high-performance computing. The company highlighted developments in DRAM, NAND, enterprise storage, advanced packaging, and semiconductor manufacturing.

Samsung’s opening keynote, titled “Driving the Wave of AI Revolution: 3D Innovations in Memory & Storage Architecture,” focused on using three-dimensional memory structures to improve system performance, power efficiency, and thermal management. Jin-Yub Lee, executive vice president and head of Flash Product & Technology, and Kyungryun Kim, vice president and project leader of the DRAM Design Team, discussed the company’s roadmap for future memory architectures.

The company displayed about 30 technologies in a booth designed to resemble an AI cloud server. Key demonstrations included concept models for zHBM and zNAND-O, V10 Bonding V-NAND, HBM4E, HBM5, LPDDR5X-PIM, and enterprise SSD platforms including the PM1763 and BM1773.

zHBM Integrates Memory Directly Above AI Accelerators

Samsung presented zHBM as a future high-bandwidth memory architecture that vertically stacks HBM directly above an AI accelerator. This differs from conventional designs in which HBM packages are positioned beside the processor.

Placing memory closer to the accelerator reduces the distance data must travel. Samsung said the approach aims to increase bandwidth, reduce power consumption, and support data movement needs of large-scale AI training and inference.

According to the company, an interface system using zHBM could deliver about eight times the performance of HBM5. The architecture is expected to provide over 10 times the memory density of HBM5, three times greater energy efficiency, and reduce thermal resistance by more than 50%.

zHBM is designed to support customer-specific configurations. Custom intellectual property could be integrated into the interlayer between the memory stack and AI accelerator, allowing system designers to tailor capacity and accelerator functionality for specific workloads.

zNAND-O Targets Edge AI Workloads

Samsung introduced zNAND-O, a high-performance NAND concept based on the company’s V-NAND technology. The architecture comes in four-layer and eight-layer configurations and is designed to improve space efficiency, I/O performance, and latency.

The company positioned zNAND-O for edge AI systems that process large datasets with minimal delay. By improving local storage performance, the architecture could support real-time applications where data cannot always be transferred to a centralized data center for processing.

V10 BV-NAND Moves Beyond 400 Layers

Samsung introduced V10 BV-NAND, a Bonding V-NAND architecture that uses wafer bonding technology to stack memory cells, unveiled as an industry first. The architecture stacks more than 400 layers, the highest Samsung has disclosed for its V-NAND line.

Samsung said V10 BV-NAND increases memory density by about 58% compared with V9. In addition to increasing capacity, the architecture aims to improve read, write, and I/O performance while reducing energy consumption.

The announcement comes 13 years after Samsung introduced the industry’s first V-NAND technology at the 2013 Flash Memory Summit. The company is targeting V10 BV-NAND for high-capacity, high-performance storage in future AI systems and other data-intensive applications.

HBM4E, HBM5, and LPDDR5X-PIM Extend the AI Memory Portfolio

Samsung presented HBM4E samples and an HBM5 model as part of its roadmap for next-generation AI accelerators. The company began the industry’s first mass production of HBM4, built on its 1c DRAM and 4 nm base die technologies, in February, and in May became the first to ship HBM4E samples to global customers.

The company also demonstrated LPDDR5X-PIM, which it describes as the industry’s first LPDDR memory with processing-in-memory technology. The design performs selected data-processing operations within the memory itself, reducing data movement between memory and processor. This can improve efficiency and lower power consumption for suitable workloads.

Samsung’s enterprise storage demonstrations included the PCIe Gen6 PM1763, which entered mass production in July, and the BM1773, both intended to support the growing storage requirements of AI data centers. These products complement the company’s memory roadmap by addressing the high-capacity and performance requirements associated with AI training data, model repositories, and inference workloads.

Samsung Promotes Integrated AI Infrastructure Development

Samsung positioned itself as the only integrated device manufacturer with capabilities spanning memory, foundry, and advanced packaging, presenting the combination as a one-stop platform for AI semiconductor development. The integrated model covers product design, semiconductor manufacturing, packaging, and mass production.

The approach aims to reduce the number of development stages between design and production while enabling tighter coordination between memory, processing, and packaging technologies. Samsung said this can help customers shorten development cycles and optimize performance and power efficiency for specialized AI systems.

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IBM and three research partners, the University of Chicago, Algorithmiq, and Qedma, have published separate quantum-computing studies focused on a common barrier to quantum advantage claims: establishing confidence in results that classical systems cannot directly reproduce.

The work spans encoded logical circuits, quantum-material simulations, and error-mitigated many-body physics. In each case, IBM Quantum Heron processors were used to run workloads that the participating teams reported exceeded the practical capabilities of leading classical simulation approaches. The studies and underlying results have been released through IBM’s Quantum Advantage Tracker for continued benchmarking.

The University of Chicago collaboration demonstrated a structured alternative to random circuit sampling, a common quantum-advantage benchmark that becomes difficult to validate as circuit complexity increases. The technique, which IBM calls doped Clifford sampling, embeds a Clifford circuit in a spacetime code and then strategically adds non-Clifford T gates, making the computation classically hard while preserving the syndrome checks needed to detect errors mid-execution. The paper is titled “Sampling hard circuits with verifiably high fidelity.”

The experiment executed 70 logical qubits, running 2,415 logical two-qubit operations and 468 logical T gates, both of which are measures of circuit complexity. IBM and the university report effective logical error rates roughly ten times lower than the underlying physical error rates, which is what allowed high circuit fidelity at those gate counts. The quantum computation finished in approximately 15 minutes, while the researchers said leading classical simulation approaches faced prohibitive runtimes. IBM describes it as one of the world’s largest known error correction demonstrations, and the result matters because it pairs a beyond-classical workload with a statistical lower bound on execution fidelity.

“We are now firmly in the quantum advantage era,” said Jay Gambetta, Director of IBM Research and IBM Fellow. “We have demonstrated a quantum computation beyond the practical reach of classical computers that establishes, with statistical confidence, a lower bound on how faithfully it was executed. This milestone gives scientists, developers, and businesses a new foundation for trusting quantum computers as they scale to problems far beyond what we can achieve classically.”

Algorithmiq’s study used an IBM Quantum Heron processor to simulate a heterogeneous quantum material, a model built to represent systems with irregular local properties, interfaces, and tunable microscopic couplings. Those effects matter for materials such as catalysts and battery electrolytes, where local disorder alters the movement of energy, particles, and information. The team developed a quantum algorithm to estimate the operator Loschmidt echo, a quantity that tracks how information spreads through such systems, and ran it on 56 qubits.

The workload was first published through the Quantum Advantage Tracker eight months ago, and IBM and Algorithmiq say no classical method has reliably reproduced results across the full problem regime since. Methods from at least three leading classical simulation groups produced predictions that conflicted with each other and with the quantum result. Rather than relying on an unavailable exact answer, the team applied controlled noise injection, modified gate calibrations, and device-noise modeling, and executed across what IBM describes as effectively five quantum computers with different noise profiles, testing whether the quantum result remained stable as noise conditions changed.

Algorithmiq also released monoprop, a benchmark package based on its classical molecular-ground-state simulation methods. The software is intended to allow external researchers to test future quantum-advantage claims against available classical techniques.

“This collaboration with IBM has realized an idea first proposed by Richard Feynman in 1982,” said Matteo Rossi, co-founder and CTO of Algorithmiq. “By simulating quantum matter using a digital quantum processor built from the same physics, we’re able to give researchers a tunable, physically interesting model open to anyone who wants to try to disprove it classically. It is a demanding test case, and it has withstood open challenge for eight months and counting.”

Qedma, IBM, RIKEN, and BlueQubit reported a third study using Qedma’s Quantum Error Suppression and Error Mitigation (QESEM) software on IBM Quantum Heron hardware to model long-lived quantum dynamics in a two-dimensional Floquet Ising system, which physicists use to study how a material’s magnetic properties evolve under rhythmic external driving. Qedma claims this is the first time quantum advantage has been achieved using commercially available hardware and software, with both the Heron system and QESEM available on the cloud. The companies point toward applications in ultrafast optoelectronics and light-induced superconductors.

IBM Quantum 133 Qubit HERON

The team reported simulations involving up to 74 qubits. It compared quantum results with several classical methods, including runs on RIKEN’s Fugaku supercomputer and simulations from BlueQubit. At the largest scale tested, the classical approaches did not consistently agree, while the error-mitigated quantum results showed persistent oscillatory behavior.

Qedma’s validation process first compared an unbiased error-mitigation method with classical calculations, in which the latter remained reliable. The researchers then benchmarked a more scalable mitigation method against the validated results before scaling up the workload to larger systems and longer execution times. The study also evaluated behavior on separate quantum hardware, including Quantinuum trapped-ion systems, to help distinguish simulated physics from device-specific artifacts.

Taken together, the three studies move the discussion of quantum advantage beyond runtime comparisons alone. They focus on reproducibility, error characterization, cross-platform validation, and open benchmarking, all of which will be required before quantum systems can be treated as reliable instruments for scientific computing workloads that exceed classical simulation limits.

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Supermicro has introduced an expanded rack portfolio for high-density AI and other mission-critical data center deployments. The lineup includes rack options based on NVIDIA MGX platforms, Open Compute Project Open Rack v3 (ORv3), and conventional EIA 19-inch designs, with configurations designed to support liquid-cooled GPU clusters and rack-scale infrastructure.

The new systems are part of Supermicro’s Data Center Building Block Solutions, or DCBBS, portfolio. The company is positioning the racks as validated infrastructure components that can be delivered pre-integrated for faster deployment, rather than requiring customers and integrators to assemble compute, networking, power, and cooling systems on site.

Charles Liang, president and CEO of Supermicro, put the scale behind it: “Our manufacturing scale enables us to deliver up to 3,000 of these advanced racks per month, including 2,000 liquid-cooled racks from our facilities around the world for immediate deployment into existing and new data centers. The racks are Plug-and-Play ready for immediate installation in the customer’s data center.” Supermicro also says the racks ship in shock- and vibration-tested crates.

The racks use a reinforced chassis rated for static loads up to 5,500 pounds (2,500 kg). This is intended to accommodate dense GPU servers, power equipment, integrated busbars, cooling distribution hardware, and related networking components. Supermicro also cites seismic and vibration testing, including GR-63-CORE Zone 4 testing, for infrastructure expected to operate in demanding or regulated environments.

Liquid cooling support is central to the design. The racks integrate with in-rack and in-row CDUs, sidecars, rear-door heat exchangers, and liquid cooling manifolds. Dedicated, separated pathways handle coolant supply and return lines, which Supermicro says improves routing efficiency and serviceability while keeping power and network cabling completely isolated to prevent signal interference.

Ten rack models make up the series, spanning 44OU, 48U, 48OU, and 52U configurations, which Supermicro says are ready for same-day data center integration:

• NVIDIA Vera Rubin/GB300 MGX platforms: Available in 48U and 52U racks, with 600 mm and 750 mm width options. These configurations include integrated busbars for high-density power delivery.
• OCP ORv3 platforms: Available in 44OU and 48OU configurations using the 21-inch Open Rack standard. These racks also include integrated busbars and are designed for ORv3-based modular compute and power architectures.
• EIA-standard platforms: Available in 48U and 52U configurations using the conventional 19-inch rack format. These systems provide an option for organizations standardizing on traditional enterprise rack infrastructure.

Supermicro’s DCBBS model supports deployment across individual servers and network components, as well as fully integrated racks and larger data center installations. The portfolio also includes associated integration services, software, and support intended to provide a single infrastructure framework for AI cluster deployments.

The entire Supermicro Rack Series is available now, shipping worldwide from the company’s manufacturing facilities in Silicon Valley, the Netherlands, and Taiwan.

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ScaleFlux has introduced an AI-optimized SSD platform designed for NVIDIA CMX and other inference architectures that use SSDs as a shared KV-cache tier beyond GPU HBM and host DRAM. The platform combines high-endurance SSD hardware, Flexible Data Placement (FDP) support, and workload telemetry intended to improve data placement, reduce write amplification, and extend effective endurance in high-churn inference environments.

The platform addresses three storage challenges with offloaded KV cache: characterizing real-world workload behavior, separating data by lifecycle, and sustaining heavy write activity without using excess flash capacity to absorb writes.

Long-context inference, shared-prefix reuse, agentic application flows, and retained idle sessions increase the volume of reusable runtime state stored outside GPU memory. Unlike conventional enterprise workloads, KV-cache blocks may be written frequently, retained for varying periods, reactivated after inactivity, and invalidated asynchronously across sessions, workers, and tenants. These patterns increase garbage collection activity and write amplification when data with incompatible lifecycles share the same flash blocks.

ScaleFlux’s high-endurance architecture is designed to deliver 7 to more than 10 effective drive writes per day at five years for KV cache workloads, with the company noting that effective endurance depends on workload characteristics, FDP utilization, and device configuration. Higher effective endurance reduces the raw flash capacity operators must deploy purely to absorb write traffic, leaving more installed capacity available to hold active KV cache and other AI runtime state. ScaleFlux calls that overhead the “endurance tax,” and reducing it is the platform’s core economic argument.

The SSD platform supports over 200 FDP write streams per drive. This lets inference software group data by lifecycle, session, tenant, shared-prefix classification, ownership, or reuse behavior before placing it on flash media. The goal is to write data with similar invalidation patterns together, reducing internal data movement during garbage collection and limiting interference across data classes.

In preliminary controlled testing, ScaleFlux measured more than a twofold reduction in write amplification using lifecycle-aware FDP placement compared with a baseline placement configuration. The company notes that actual results depend on workload characteristics, lifecycle classification, software integration, and device configuration.

“AI inference infrastructure needs SSDs that provide more than additional capacity,” said Hao Zhong, CEO and co-founder of ScaleFlux. “Infrastructure teams need to understand how KV workloads affect the drive, separate data according to lifecycle, and sustain high write rates without deploying excess capacity simply to dilute writes. ScaleFlux brings workload intelligence, scalable FDP placement, and 7-10+ effective DWPD together in one AI-optimized SSD platform.”

At the software and telemetry layer, ScaleFlux Context-Insight SSD shows how KV-cache policies affect SSD operation. The platform captures latency, queue depth, throughput, request-size distribution, data age, write-to-first-read intervals, read reuse, NAND write volume, garbage collection movement, and write amplification.

Context-Insight can operate in SSD-only mode for initial workload analysis without changes to upper software layers. With deeper integration, it correlates SSD telemetry with application metadata, including session IDs, worker or tenant identifiers, shared-prefix IDs, KV-block ownership, lifecycle state, and key-to-block mappings. This lets operators associate latency, endurance consumption, and write amplification with specific workload classes instead of treating the SSD as an opaque shared resource.

ScaleFlux positions the platform as a complement to NVIDIA’s recently announced CMX Context Memory Storage Platform, which provides a shared, pod-level context tier for high-speed KV cache access and reuse. The pitch is aimed at AI factory operators: CMX handles the context tier, while ScaleFlux addresses the endurance, data placement, and write amplification challenges specific to the underlying SSDs.

“As AI inference systems extend KV cache beyond GPU Memory and DRAM, understanding the behavior and requirements of the SSD tier becomes increasingly important,” said Jason Hardy, vice president of storage technology at NVIDIA. “Our engagement with ScaleFlux is helping characterize how KV cache offload affects storage requirements for latency, endurance, and write amplification, contributing to the broader storage ecosystem around NVIDIA CMX.”

The company is developing a trace-driven simulator that models KV-cache movement across GPU HBM, host memory, and SSD tiers. The simulator generates replayable SSD traces to evaluate placement, eviction, and lifecycle-grouping policies under controlled conditions.

ScaleFlux plans to showcase the platform at FMS, covering Context-Insight workload analysis, KV metadata correlation, lifecycle-aware FDP placement, write amplification reduction, and high-endurance operation for write-intensive KV cache workloads. The company has a substantial presence at the show: ScaleFlux said in July that its experts would lead seven presentations there, including a keynote co-delivered with NVIDIA on memory solutions for scaling the AI data pipeline.

The platform announcement caps a busy stretch of silicon news. Two days earlier, ScaleFlux unveiled two PCIe Gen6 parts it will introduce at the same show: the FC6116 NVMe SSD controller and the MC600 CXL 3.2 Type 3 memory controller. ScaleFlux rates the FC6116 at up to 28 GB/s sequential read and 25 GB/s sequential write, up to 7 million 4K random read IOPS and more than 1 million sustained 4K random write IOPS, under 9W active controller power, with support for TLC, QLC, and SLC NAND up to 256TB across E1.S/L, E3.S/L, and U.2/3. The MC600 draws under 9W typical in a Gen6 x8 configuration and handles quad-channel DDR5 or dual-channel DDR4 with up to 2TB of DDR5, a dual-generation capability ScaleFlux positions as a way to carry existing DDR4 into a CXL deployment. Both begin sampling with key customers in Q4 2026.

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