Direct:
Ramping a leading-edge node at five fab phases in its first year is effectively unprecedented for a foundry. That is what TSMC (TSM) laid out at its 2026 Technology Symposium: N2 going into volume at Fab 20 in Hsinchu and Fab 22 in Kaohsiung at the same time, with more phases queued behind them. First-year N2 wafer output is targeted around 45% above where N3 started in 2023, which puts year-end capacity somewhere near 90,000 wafer starts per month. Estimates run as high as 140k, so treat the exact figure as soft. For comparison, Intel's 18A line at Fab 52 is believed to top out around 40,000 WSPM.
N2 and A16 capacity is set to grow at a 70% CAGR through 2028, which points to hundreds of thousands of WSPM by the end of that run. TSMC has roughly doubled its construction pace, building or converting nine fab phases a year across 2025 and 2026 against the four to five it averaged before.
What lets parallel ramps work instead of multiplying the risk is the coordination layer. TSMC credits its “One Team” structure and what it calls a Super Manufacturing Platform that runs multiple fabs off identical recipes, tooling, and yield-management flows, conceptually close to Intel's old “Copy Exactly.” The claimed payoff is faster technology transfer and a better N2 yield-learning curve than N3 saw, even with the jump to gate-all-around nanosheets. Running five phases at once also spreads risk: a contamination event or a quake at one site does not take the whole node offline.
Packaging is the other half of the story, and the tighter constraint right now. CoWoS capacity is on an 80% CAGR through 2027, SoIC on 90%. AP7 in Chiayi is being built out as the largest SoIC campus, aimed at Nvidia's (NVDA) Feynman generation, while AP8, a converted Innolux LCD fab, is expected to clear 40,000 CoWoS wafers a month by late 2026.
This is leading-edge logic and packaging, not the storage and memory most of you buy, but it is where the capacity is going. Apple (AAPL), AMD (AMD), Nvidia, and Qualcomm (QCOM) are the names lined up for N2 and the packaging behind it, and wafer shipments for AI accelerators are projected to rise 11x between 2022 and 2026. When you wonder why leading-edge logic, HBM, and advanced packaging are all constrained at once, this is a big part of why.
Drafted with AI assistance against parallel reporting.
Sources:
- Tom's Hardware (Anton Shilov), June 2026
- Focus Taiwan / CNA, April 2026
- Electronics Weekly, May 2026
- CNBC, April 2026
- TrendForce, March 2026
- DigiTimes, January 2026
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