Direct:
The bottleneck in large AI clusters has moved off the chip and onto the wire between chips. At 224 Gbps per lane, passive copper barely reaches a meter, and interconnect is eating a fast-growing share of cluster power. That is the pressure behind the shift everyone now frames as chip-centric to interconnect-centric, and TSMC (NYSE: TSM) is positioned to supply the capacity for the answer.
The vehicle is COUPE, TSMC's co-packaged optics platform, which is ramping toward volume production this year. Each optical engine targets 1.6 Tbps in each direction, eight 200G PAM4 lanes per side, built by stacking photonic ICs under logic with SoIC-style packaging. The capacity question is the real one. SoIC monthly output is reportedly headed toward 30,000 to 40,000 wafers by the end of 2026, and photonics is now bidding for the same advanced-packaging complex, CoWoS and SoIC, that GPU and HBM integration already strains. Securing those slots ahead of the crunch is crucial.
Nvidia (NASDAQ: NVDA) is a named first customer and fast-forwarded its optics roadmap by roughly five years at GTC 2026. Feynman in 2028 is the inflection, with NVLink switches carrying co-packaged optics and Kyber-generation scale-up domains stretching toward 1,152 GPU packages. Broadcom (NASDAQ: AVGO) is the other early customer, attaching CPO to its Tomahawk switches.
Copper still has a job, and the through-2028 framing runs both directions. Hock Tan has been explicit that copper stays viable inside the rack through 2028, carrying ultra-short links as per-lane rates climb toward 400G, and Nvidia's own roadmap pairs a copper scale-up option (Kyber) with the CPO version rather than replacing it. The realistic picture is co-existence. Copper holds the short intra-rack hops on cost and reliability, optics takes the longer scale-up and scale-out reach. Widespread CPO before 2028 still runs into manufacturing yield and field-maintenance problems nobody has fully solved.
For anyone tracking memory and GPU supply, this lands on the same constraint they already watch. Photonics is now pulling on the TSMC advanced-packaging queue that gates HBM and AI accelerators, which is one more claim on the capacity sitting upstream of pricing.
Drafted with AI assistance against parallel reporting.
Sources:
- DIGITIMES Asia (Emily Kuo, May 27 / June 1 2026): copper limits and foundry silicon photonics capacity through 2028, chip-centric to interconnect-centric framing
- TSMC 2026 Technology Forum coverage / BigGo / TrendForce (2025-2026): COUPE volume production timeline, 1.6 Tbps optical engines on eight 200G PAM4 lanes per side, SoIC capacity toward 30K-40K wafers/month by end of 2026, Broadcom and Nvidia as first customers
- SemiEngineering / Synopsys (2025-2026): 224 Gbps copper reach under one meter, rising interconnect power share, all-optical interconnect within five years
- Tom's Hardware / HPCwire / The Register (March-April 2026): Nvidia GTC 2026 roadmap, Feynman 2028, Kyber and Kyber CPO scale-up, NVLink optical switches, NVL1152 scale-up domain
- DIGITIMES / SDxCentral (March 2026): Broadcom CEO Hock Tan on copper viable through 2028 for ultra-short in-rack links, copper and optics as co-existing rather than substitutes
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