An Ideal Approach to 3D NAND Flash Design for Ultra-High IOPS SSDs (>100M) with Low-Latency (<=5us), Fine-Grained (Page Size=512B), and a Novel MB-level Embedded DRAM to support On-Chip NAND Managements

Macronix paper proposing a redesign of (3D) SLC NAND for ultra-high IOPS (>100M). Target is very low read latency (<5µs) with fine-grained 512B pages. Storage tech that would fit between main memory (DRAM) and normal non-volatile (SSD) in the memory hierarchy, and yes that's a role once meant to be filled by Optane.

• CuA + CbA to help reduce latency and increase plane count.
• Much smaller block size (<1MB) than what modern 3D NAND uses. Improves read latency, reduces potential wear.
• True 512B page size. Can improve read speeds by up to 10x over pSLC.
• Embedded DRAM in the NAND chip. This on-chip cache can handle metadata (L2P/FTL), act as a write and wear-leveling buffer. Offloads work from the SSD controllers.
• Article claims each 32-plane chip can deliver ~6.4M IOPS at 3.2 GB/s at <5µs latency. An SSD with 16 chips can surpass 100M IOPS.
• Goal is to have NAND fit into the memory-class storage (MCS) paradigm. Can scale to 64 planes.