Direct:
TSMC (TSM) is using its 2026 Technology Symposium circuit to point the audience at one acronym: COUPE. Co-COO Kevin Zhang framed it as the keyword for what comes next in AI silicon at the May 14 Hsinchu event, echoing the same emphasis from the Santa Clara stop in April. COUPE is not a node, not a transistor architecture, not an HBM generation; it's a co-packaged optics platform, and TSMC is putting it center stage.
The acronym stands for Compact Universal Photonic Engine. The pitch: stack a photonic IC and an electrical IC using SoIC bonding, drop the resulting optical engine inside the package next to the switch ASIC or GPU, and stop dragging signals across centimeters of lossy PCB trace. TSMC's published claim for the on-substrate version is 2x power efficiency and 10x lower latency versus a pluggable on the board, with broader internal benchmarks running higher. First-gen COUPE for small-form-factor pluggables was targeted for qualification in 2025; the on-substrate true CPO version is set to begin production this year, with CoWoS-integrated CPO as the second-gen step.
Nvidia (NVDA) has Quantum-X InfiniBand photonics switches in early 2026 and Spectrum-X Ethernet photonics switches in 2H 2026, both leaning on TSMC's SoIC infrastructure. Broadcom (AVGO) is on its third-gen Tomahawk 6-Davisson CPO scale-out part and developing a fourth. Marvell (MRVL), through its Celestial AI acquisition, has guided to a $500M CPO run rate by Q4 FY28 doubling to $1B a year later. Nvidia put $2B each into Coherent (COHR) and Lumentum (LITE) to lock in laser supply. TrendForce now models the AI-focused optical transceiver market at $26B in 2026, up 57% year-over-year from $16.5B in 2025.
There's a Taiwan supply-chain layer worth naming. TSMC's SoIC monthly capacity is reportedly headed to 30,000-40,000 wafers by end of 2026 per Commercial Times sourcing. LuxNet (4979.TWO) and TrueLight are scaling 800G optics and CW lasers for the silicon-photonics path. UMC (UMC) licensed imec's iSiPP300 photonics process with risk production penciled in for 2026-2027. AMD (AMD) is reportedly building a silicon photonics R&D center in southern Taiwan.
The investable angle is not client devices, it is advanced packaging and optical-component capacity. COUPE adds pressure across that ecosystem, particularly as it moves from on-substrate CPO into CoWoS-integrated CPO and starts sharing roadmap real estate with accelerator interposers. The next AI bottleneck is the wire between chips, and TSMC intends to own the optical packaging layer where scale-out hits its power, latency, and bandwidth-density limits.
Sources used:
- DigiTimes, “TSMC SVP: better AI days lie ahead, remember the keyword 'COUPE'” (May 14, 2026)
- SemiWiki, TSMC 2026 Technology Symposium coverage (Apr 2026)
- Electronics Weekly, “TSMC introduces A13 node; says no need for high-NA through 2029” (Apr 2026)
- TrendForce, “Silicon Photonics Race Intensifies as TSMC Targets 2026 COUPE Production, Samsung Eyes 2029 CPO Turnkey” (Apr 1, 2026)
- TrendForce, “AI Optical Transceiver Market to Reach US$26 Billion in 2026” (Apr 2026)
- TrendForce, “AMD Reportedly to Set up Silicon Photonics R&D Center in Southern Taiwan” (Oct 2025)
- TrendForce, “UMC Licenses imec's iSiPP300” (Dec 2025)
- Tom's Hardware, “Nvidia outlines plans for using light for communication between AI GPUs by 2026” (Aug 2025)
- IO Fund, “Inside Nvidia's $4B Optical Strategy” (May 2026)
- 3D InCites IFTLE 642, TSMC CoWoS + COUPE technical deep-dive (Oct 2025)
- Nvidia.com, Silicon Photonics Networking product page
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