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Chinese Firm Naura Claims Big Breakthrough That Could Enable CXMT To Overcome EUV Sanctions & Make 3D DRAM Chips

A digital illustration of a stacked, neon-lit processor concept on a futuristic circuit board.

China's Naura Technology Group, a key domestic semiconductor manufacturing equipment provider, claims to have developed a two-step etch process for manufacturing 3D DRAM chips. 3D DRAM chips are the next generation of DRAM technology as they seek to overcome the constraints of current chips when it comes to cell density. A paper published by Naura in the IEEE journal explains progress made in etching uniformly across the 64 layers of 3D DRAM to shift the focus to vertical manufacturing instead of the horizontal constraints encountered by non-EUV lithography. Chinese Chip Equipment Manufacturer Naura Details Breakthrough In Semiconductor Etch Engineering That […]

Read full article at https://wccftech.com/chinese-chip-making-equipment-firm-naura-claims-big-breakthrough-that-could-enable-cxmt-to-overcome-euv-sanctions-make-3d-dram-chips/

AMD Says A Hybrid-Bonded 3D DRAM Is 17x More Energy Efficient Than An HBM Stack That Relies On Microbumps, But Thermal Hurdles Block Commercialization

A digital illustration of a stacked, neon-lit processor concept on a futuristic circuit board.

The silicon industry has arrived at a consensus that the HBM pathway to unlock incremental AI compute is stalling, especially as converting silicon wafers into an HBM stack yields far less usable capacity than commodity DRAM, prompting the wider industry to start experimenting with SRAM-only decode, Processor-In-Memory (PIM) within LPDDR, CXL pooling, and 3D DRAM. Of course, it is the 3D DRAM architecture that is considered somewhat of a panacea at the moment, as highlighted by AMD's recent admission as to its phenomenal energy efficiency. Even so, odious hurdles continue to prevent the commercialization of this promising technology. AMD has […]

Read full article at https://wccftech.com/amd-says-a-hybrid-bonded-3d-dram-is-17x-more-energy-efficient-than-an-hbm-stack-that-relies-on-microbumps-but-thermal-hurdles-block-commercialization/

CXMT Swaps Silicon for Hafnium Inside Its DRAM Transistors, Unlocking A Path To The 1a Node And Beyond, As Its Capacity To Hit 800,000 Wafers Per Month By 2031

Samsung reportedly wants to use CXMT DRAM chips to enter China

CXMT may have just taken its biggest leap towards the 1a DRAM process and beyond by successfully applying an advanced material within DRAM transistors that curbs leakage current, paving the way for its DRAM fabrication process to graduate to the more advanced nodes. CXMT is now using the High-k Metal Gate (HKMG) technology within its DRAM transistors As components shrink to the nanometer scale, standard silicon dioxide (SiOβ‚‚) insulation layers typically lose effectiveness, becoming so thin that the current starts leaking straight through them via quantum tunneling. To overcome this process miniaturization constraint, CXMT is now apparently using High-k Metal […]

Read full article at https://wccftech.com/cxmt-swaps-silicon-for-hafnium-inside-its-dram-transistors-unlocking-a-path-to-the-1a-node-and-beyond-as-its-capacity-to-hit-800000-wafers-per-month-by-2031/

d-Matrix’s Raptor 3D DRAM Achieves SRAM-Class Bandwidth at 1/10th the HBM Power by Dropping PHY & Fusing DRAM Beneath the Compute

The image features the d-Matrix logo and an illustration of a circuit in the shape of a brain, with the text 'Raptor: The First 3D-DRAM Accelerator for Generative Inference'.

d-Matrix proposes 3D DRAM as a solution to the rising AI data problem using stacked memory to deliver SRAM-Like bandwidth with magnitudes higher efficiency than HBM. The Time For 3D DRAM Is Now, Says d-Matrix, As It Unveils its "Raptor" 3D DRAM Solution With SRAM-Class Bandwidth As AI model sizes and KV cache continue to expand, capacity and bandwidth constraints become more visible. So far, all major DRAM manufacturers are working toward next-gen solutions that stack logic with DRAM, but d-Matrix says "The Time For 3D DRAM" is now. Today, there are two leading memory technologies for AI workloads: SRAM […]

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Apacer CEO Warns That Commodity DRAM Supply Will Fall By 70% In 2027, Echoing A Doomsday Take From The CEO Of SK hynix

SK hynix working on a new DRAM architecture to bring the real on-device AI to smartphones

It seems hell hath no fury like a commodity DRAM chip spurned. As HBM continues to hog DDR wafers, the supply of DRAM might plummet as much as 70 percent in 2027, according to the CEO of Apacer, which echoes recent pronouncements from the CEO of SK hynix. The CEO of Apacer expects the supply of commodity DRAM to fall off the proverbial roof in 2027, echoing pronouncements from the CEO of SK hynix, who thinks "next year will be the worst year in the industry's history from the supply perspective" According to the CEO of Apacer, C.K. Chang, DRAM […]

Read full article at https://wccftech.com/apacer-ceo-warns-that-commodity-dram-supply-will-fall-by-70-in-2027-echoing-a-doomsday-take-from-the-ceo-of-sk-hynix/

China Develops Its First 3.5D β€œInfinity Chiplet” & 3D DRAM Tech As It Tackles External HBM Constraints Through Domestic AI Supply Chain

China Develops Its First 3.5D "Infinity Chiplet" & 3D DRAM Tech As It Tackles External HBM Constraints Through Domestic AI Supply Chain

China's DFSX is working on fueling its domestic AI supply chain with next-gen 3.5D "Infinity Chiplet" architectures & 3D DRAM technologies. DFSX Is Working on China's First DF1000 AI Accelerator With 3D DRAM Technology, Also Unveils 3.5D+ Packaging DFSX recently hosted a presentation where they announced China's first 3D AI chip that is built entirely using China's domestic supply chain. There is a lot to unpack here, but the key product is the DF1000, which is a software-defined near-in-memory computing AI accelerator that will be used by domestic AI and tech firms. DF1000 - China's First 3D DRAM-Powered AI Accelerator […]

Read full article at https://wccftech.com/china-develops-first-3-5d-infinity-chiplet-3d-dram-tech-as-it-tackles-external-constraints/

China’s YMTC Fires Back at US Chip Restrictions with Three New Fabs Set to Double Its Wafer Output

An aerial view of the Yangtze Memory Technologies factory with a large logo and the text 'YANGTZE MEMORY' in the top left corner.

As the United States continues to hammer down trade restrictions on China, YMTC has decided to uplift the chipmaking capacity by building new fabs. China & US Trade Wars Continue, In the Midst, YMTC Decides To Double Its Production Capacity With Two Brand New Chipmaking Factories The semiconductor industry is currently facing a trade war between two giants. On one hand, there's the United States, and on the other, there's China. From export restrictions to the banning of necessary tools that are required for making chips, the United States is trying to ensure that China doesn't get bleeding-edge materials and […]

Read full article at https://wccftech.com/china-to-double-chip-making-capacity-with-three-new-ymtc-fabs-tackle-us-restrictions/

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